Merge commit 'b611ab7090264b5a01181aa21a436f4bce2ef9bc'

* commit 'b611ab7090264b5a01181aa21a436f4bce2ef9bc':
  arm64: configs: optimize latency for PREEMPT_RT
  ARM: configs: add rockchip_rt.config for PREEMPT_RT
  drm/bridge: synopsys: dw-hdmi-qp: Fix hdmi is enabled twice during boot
  drm/rockchip: vop2: only esmart/cluster win0 need to manage done bit
  arm64: dts: rockchip: rv1126bp: set init-freq to 600M for npu
  arm64: dts: rockchip: rv1126b: adjust opp-supported-hw for npu
  media: rockchip: vicap fixes size error of rgb888
  rtc: s35390a: fix the issue where the alarm clock interruption cannot be triggered
  drm/bridge: synopsys: dw-hdmi-qp: Clear mode list when hdmi plug out
  soc: rockchip: fiq_debugger: fix dts property 'rockchip,irq-mode-enable'

Change-Id: I813202127d9f4e087f180f25368d16b78c6e95d1
This commit is contained in:
Tao Huang
2025-07-12 19:27:01 +08:00
9 changed files with 139 additions and 20 deletions

View File

@@ -0,0 +1,31 @@
# CONFIG_ARM_PSCI_CPUIDLE is not set
# CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ is not set
# CONFIG_CGROUP_CPUACCT is not set
# CONFIG_CGROUP_SCHED is not set
# CONFIG_CPU_FREQ_TIMES is not set
# CONFIG_CPU_FREQ_THERMAL is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_FTRACE is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
# CONFIG_MALI_BIFROST_ENABLE_TRACE is not set
# CONFIG_MALI_BIFROST_SYSTEM_TRACE is not set
# CONFIG_PSI is not set
# CONFIG_PERF_EVENTS is not set
# CONFIG_PROFILING is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_SCHED_INFO is not set
# CONFIG_SWAP is not set
# CONFIG_TASKSTATS is not set
# CONFIG_ZRAM is not set
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
# CONFIG_ARCH_MULTIPLATFORM is not set
# CONFIG_VMAP_STACK is not set
# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
# CONFIG_HARDEN_BRANCH_HISTORY is not set
# CONFIG_COMPACTION is not set
# CONFIG_MIGRATION is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
CONFIG_HZ_PERIODIC=y
CONFIG_HZ_1000=y
CONFIG_PREEMPT_RT=y
CONFIG_VDSO=y

View File

@@ -3337,24 +3337,24 @@
opp-microvolt-L1 = <875000 875000 1050000>;
};
opp-700000000 {
opp-supported-hw = <0xf7 0xffff>;
opp-supported-hw = <0xff 0xffff>;
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <850000 850000 1050000>;
opp-microvolt-L0 = <900000 900000 1050000>;
opp-microvolt-L1 = <875000 875000 1050000>;
};
opp-800000000 {
opp-supported-hw = <0xf7 0xffff>;
opp-supported-hw = <0xff 0xffff>;
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <925000 925000 1050000>;
};
opp-900000000 {
opp-supported-hw = <0xf7 0xffff>;
opp-supported-hw = <0xff 0xffff>;
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <975000 975000 1050000>;
};
opp-950000000 {
opp-supported-hw = <0xf7 0xffff>;
opp-supported-hw = <0xff 0xffff>;
opp-hz = /bits/ 64 <950000000>;
opp-microvolt = <975000 975000 1050000>;
opp-microvolt-L0 = <1000000 1000000 1050000>;

View File

@@ -8,6 +8,10 @@
/ {
};
&npu_opp_table {
rockchip,init-freq = <600000>;
};
&rgb {
/*
* RV1126 compatible pin output mode 0.

View File

@@ -1,5 +1,25 @@
# CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ is not set
# CONFIG_ARM_PSCI_CPUIDLE is not set
# CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ is not set
# CONFIG_CGROUP_CPUACCT is not set
# CONFIG_CGROUP_SCHED is not set
# CONFIG_CPU_FREQ_TIMES is not set
CONFIG_NO_HZ_FULL=y
# CONFIG_CPU_FREQ_THERMAL is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_FTRACE is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
# CONFIG_MALI_BIFROST_ENABLE_TRACE is not set
# CONFIG_MALI_BIFROST_SYSTEM_TRACE is not set
# CONFIG_PSI is not set
# CONFIG_PERF_EVENTS is not set
# CONFIG_PROFILING is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_SCHED_INFO is not set
# CONFIG_SWAP is not set
# CONFIG_TASKSTATS is not set
# CONFIG_ZRAM is not set
# CONFIG_MIGRATION is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
CONFIG_JUMP_LABEL=y
CONFIG_HZ_PERIODIC=y
CONFIG_HZ_1000=y
CONFIG_PREEMPT_RT=y

View File

@@ -2622,6 +2622,7 @@ dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
struct dw_hdmi_qp *hdmi =
container_of(connector, struct dw_hdmi_qp, connector);
struct dw_hdmi_qp *secondary = NULL;
struct drm_display_mode *mode;
enum drm_connector_status result, result_secondary;
mutex_lock(&hdmi->mutex);
@@ -2659,8 +2660,12 @@ out:
extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true);
handle_plugged_change(hdmi, true);
} else {
if (!hdmi->next_bridge)
if (!hdmi->next_bridge) {
drm_connector_update_edid_property(&hdmi->connector, NULL);
list_for_each_entry(mode, &hdmi->connector.modes, head)
mode->status = MODE_STALE;
drm_mode_prune_invalid(hdmi->connector.dev, &hdmi->connector.modes, false);
}
extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, false);
handle_plugged_change(hdmi, false);
}
@@ -3403,7 +3408,8 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &val);
/* if plug out before hdmi bind, reset hdmi */
if (vmode->mtmdsclock >= 340000000 && vmode->mpixelclock <= 600000000 &&
!(val & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) && !hdmi->force_kernel_output)
!(val & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) && !hdmi->force_kernel_output &&
hdmi->initialized)
hdmi->logo_plug_out = true;
}

View File

@@ -1112,6 +1112,8 @@ static inline void rk3588_vop2_dsc_cfg_done(struct drm_crtc *crtc);
static inline void vop2_cfg_done(struct drm_crtc *crtc);
static void vop2_wait_for_fs_by_done_bit_status(struct vop2_video_port *vp);
static int vop2_clk_reset(struct reset_control *rstc);
static inline bool vop2_cluster_sub_window(struct vop2_win *win);
static inline bool vop2_multi_area_sub_window(struct vop2_win *win);
static void vop2_wait_for_scan_timing_max_to_assigned_line(struct vop2_video_port *vp,
u32 current_line,
u32 wait_line);
@@ -2285,14 +2287,17 @@ static void vop2_win_disable(struct vop2_win *win, bool skip_splice_win)
}
}
vp_id = ffs(win->vp_mask) - 1;
if (vp_id >= ROCKCHIP_MAX_CRTC) {
DRM_ERROR("Unsupported vp_id: %d\n", vp_id);
return;
if (!vop2_cluster_sub_window(win) && !vop2_multi_area_sub_window(win)) {
vp_id = ffs(win->vp_mask) - 1;
if (vp_id >= ROCKCHIP_MAX_CRTC) {
DRM_ERROR("%s unsupported vp_id: %d, win->vp_mask:0x%x\n",
win->name, vp_id, win->vp_mask);
return;
}
vp = &vop2->vps[vp_id];
if (vp->reserved_plane_phy_id != ROCKCHIP_VOP2_PHY_ID_INVALID)
vp->win_cfg_done_bits |= BIT(win->reg_done_bit);
}
vp = &vop2->vps[vp_id];
if (vp->reserved_plane_phy_id != ROCKCHIP_VOP2_PHY_ID_INVALID)
vp->win_cfg_done_bits |= BIT(win->reg_done_bit);
}
if (win->left_win && win->splice_mode_right) {
@@ -7164,7 +7169,8 @@ static void vop2_win_atomic_update(struct vop2_win *win, struct drm_rect *src, s
VOP_CLUSTER_SET(vop2, win, frm_reset_en, 1);
VOP_CLUSTER_SET(vop2, win, dma_stride_4k_disable, 1);
}
vp->win_cfg_done_bits |= BIT(win->reg_done_bit);
if (!vop2_cluster_sub_window(win) && !vop2_multi_area_sub_window(win))
vp->win_cfg_done_bits |= BIT(win->reg_done_bit);
spin_unlock(&vop2->reg_lock);
}

View File

@@ -4058,7 +4058,7 @@ static int rkcif_csi_channel_init(struct rkcif_stream *stream,
channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
channel->width = channel->width * fmt->bpp[0] / 8;
if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888 && dev->chip_id < CHIP_RK3576_CIF)
channel->width /= 2;
/*
* rk cif don't support output yuyv fmt data
@@ -11218,7 +11218,7 @@ static void rkcif_dynamic_crop(struct rkcif_stream *stream)
mbus->type == V4L2_MBUS_CCP2) {
struct csi_channel_info *channel = &cif_dev->channels[stream->id];
if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888 && cif_dev->chip_id < CHIP_RK3576_CIF)
crop_x = 3 * stream->crop[CROP_SRC_ACT].left / 2;
else if (channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
crop_x = 2 * stream->crop[CROP_SRC_ACT].left;

View File

@@ -468,6 +468,45 @@ static const struct rtc_class_ops s35390a_rtc_ops = {
.ioctl = s35390a_rtc_ioctl,
};
static irqreturn_t s35390a_irq(int irq, void *dev_id)
{
int err;
char sts = 0;
char status1;
struct s35390a *s35390a = (struct s35390a *)dev_id;
struct i2c_client *client = s35390a->client[0];
rtc_lock(s35390a->rtc);
err = s35390a_read_status(s35390a, &status1);
if (err < 0) {
dev_err(&client->dev, "read status failure\n");
goto out;
}
if (status1 & S35390A_FLAG_INT2) {
/* clear pending interrupt (in STATUS1 only), if any */
err = s35390a_get_reg(s35390a, S35390A_CMD_STATUS1, &sts, sizeof(sts));
if (err < 0) {
dev_err(&client->dev, "read S35390A_CMD_STATUS1 failure\n");
goto out;
}
sts = S35390A_INT2_MODE_NOINTR | S35390A_INT2_MODE_32K;
/* disable interrupt */
err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
if (err < 0) {
dev_err(&client->dev, "clear interrupt failure\n");
goto out;
}
rtc_update_irq(s35390a->rtc, 1, RTC_AF);
}
out:
rtc_unlock(s35390a->rtc);
return IRQ_HANDLED;
}
static int s35390a_probe(struct i2c_client *client)
{
int err, err_read;
@@ -546,6 +585,18 @@ static int s35390a_probe(struct i2c_client *client)
set_bit(RTC_FEATURE_ALARM_RES_MINUTE, s35390a->rtc->features);
clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, s35390a->rtc->features );
if (client->irq > 0) {
err = devm_request_threaded_irq(&client->dev, client->irq,
NULL, s35390a_irq,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
client->name, s35390a);
if (err < 0) {
dev_err(&client->dev, "irq %d request failed, %d\n",
client->irq, err);
return err;
}
}
if (status1 & S35390A_FLAG_INT2)
rtc_update_irq(s35390a->rtc, 1, RTC_AF);

View File

@@ -67,6 +67,7 @@ struct rk_fiq_debugger {
static int rk_fiq_debugger_id;
static int serial_hwirq;
static int irq_mode;
#ifdef CONFIG_FIQ_DEBUGGER_TRUST_ZONE
static bool tf_fiq_sup;
@@ -933,7 +934,7 @@ static void rk_serial_debug_init(void __iomem *base, phys_addr_t phy_base,
res[0].start = irq;
res[0].end = irq;
#if defined(CONFIG_FIQ_GLUE)
if (signal_irq > 0)
if (irq_mode != 1 && signal_irq > 0)
res[0].name = "fiq";
else
res[0].name = "uart_irq";
@@ -1041,7 +1042,7 @@ static int __init rk_fiqdbg_probe(struct platform_device *pdev)
struct device_node *np = pdev->dev.of_node;
unsigned int id, ok = 0;
int irq, signal_irq = -1, wake_irq = -1;
unsigned int baudrate = 0, irq_mode = 0;
unsigned int baudrate = 0;
phys_addr_t phy_base = 0;
int serial_id;
struct clk *clk;