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drm/rockchip: vop2: Fix dclk_out rate calculate error in YUV420 output mode

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The K will be set 2 in YUV420 output mode, so we
don't need to handle YUV420 for DisplayPort.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I8f42536735e65c82705d58382f1db2b2994d741b
This commit is contained in:
Andy Yan
2021-11-30 19:45:51 +08:00
committed by Tao Huang
parent 27dc0c199b
commit 167ea3e2e9
1 changed files with 3 additions and 5 deletions
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8
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -5221,11 +5221,9 @@ static int vop2_calc_if_clk(struct drm_crtc *crtc, const struct vop2_connector_i
if_pixclk->rate = hdmi_edp_pixclk;
if_dclk->rate = hdmi_edp_dclk;
} else if (vcstate->output_type == DRM_MODE_CONNECTOR_DisplayPort) {
if (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420)
dclk_out_rate = v_pixclk >> 3;
else
dclk_out_rate = v_pixclk >> 2;
if_pixclk->rate = dclk_out_rate / K;
dclk_out_rate = v_pixclk >> 2;
dclk_out_rate = dclk_out_rate / K;
if_pixclk->rate = dclk_out_rate;
} else if (vcstate->output_type == DRM_MODE_CONNECTOR_DSI) {
if (vcstate->dsc_enable) {
dclk_out_rate = dclk_core_rate / K;