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Merge commit 'fc5aafdc74cb363bf1c2d69461083e455d935f25'

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* commit 'fc5aafdc74cb363bf1c2d69461083e455d935f25': (24 commits)
  ethernet: stmmac: dwmac-rk: Add macphy clock input method for rv1126b
  arm64: dts: rockchip: rv1126b-evb2-v10: Fix FEPHY clock and led
  ARM: configs: rv1126b-evb: Enable CONFIG_VIDEO_SC635HAI
  media: i2c: add sc635hai sensor driver for kernel 6.1
  media: i2c: sc450ai: add 2lane/4lane hdr config
  arm64: configs: add rk3576_vehicle_amp.config
  arm64: dts: rockchip: add rk3576-vehicle-amp
  media: rockchip: hdmirx: fix crash when get fmt
  power: supply: rk817_battery: Refactor code and update state-of-charge algorithm
  drm/rockchip: vop: Fix wrong RV1126B_CLK_CNT offset
  arm64: dts: rockchip: rv1126b: fix rtc clock
  rtc: rockchip: remove rtc test for rv1126b
  media: rockchip: aiisp: remove some spinlock
  ASoC: rockchip: pdm_v2: calculate the data shift if not set by dts on rv1126b
  thermal: rockchip: Use software ctrl mode for rv1126b
  media: rockchip: isp: fix isp35 lsc and awb error for aiisp en
  media: rockchip: isp: remove clk 600M for isp35
  ARM/dma-mapping: fix range overflow
  ARM/dma-mapping: treat address 0 of IOVA valid
  ARM/dma-mapping: increase iommu bitmap size to 64KB
  ...

Change-Id: Idc855c3ff19f089a40434356f58cbd6f8ea2682e
This commit is contained in:
Tao Huang
2025-04-03 21:03:47 +08:00
parent 338e92c0ca fc5aafdc74
commit 1f4bf45e09
30 changed files with 4935 additions and 1183 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/configs/rv1126b-evb.config
View File

@@ -55,6 +55,7 @@ CONFIG_VIDEO_SC401AI=m
CONFIG_VIDEO_SC4336=m
CONFIG_VIDEO_SC450AI=m
CONFIG_VIDEO_SC530AI=m
CONFIG_VIDEO_SC635HAI=m
CONFIG_VIDEO_SC850SL=m
CONFIG_VIDEO_TECHPOINT=m
CONFIG_WIRELESS=y

22
arch/arm/mm/dma-mapping.c
View File

@@ -821,7 +821,7 @@ static inline void __free_iova(struct dma_iommu_mapping *mapping,
unsigned int start, count;
size_t mapping_size = mapping->bits << PAGE_SHIFT;
unsigned long flags;
dma_addr_t bitmap_base;
unsigned long long bitmap_base;
u32 bitmap_index;
if (!size)
@@ -1424,7 +1424,7 @@ static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
int offset = handle & ~PAGE_MASK;
int len = PAGE_ALIGN(size + offset);
if (!iova)
if (WARN(handle == DMA_MAPPING_ERROR, "invalid iommu iova address.\n"))
return;
if (!dev->dma_coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) {
@@ -1486,7 +1486,7 @@ static void arm_iommu_unmap_resource(struct device *dev, dma_addr_t dma_handle,
unsigned int offset = dma_handle & ~PAGE_MASK;
size_t len = PAGE_ALIGN(size + offset);
if (!iova)
if (WARN(dma_handle == DMA_MAPPING_ERROR, "invalid iommu iova address.\n"))
return;
iommu_unmap(mapping->domain, iova, len);
@@ -1501,7 +1501,7 @@ static void arm_iommu_sync_single_for_cpu(struct device *dev,
struct page *page;
unsigned int offset = handle & ~PAGE_MASK;
if (dev->dma_coherent || !iova)
if (dev->dma_coherent || WARN(handle == DMA_MAPPING_ERROR, "invalid iommu iova address.\n"))
return;
page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
@@ -1516,7 +1516,7 @@ static void arm_iommu_sync_single_for_device(struct device *dev,
struct page *page;
unsigned int offset = handle & ~PAGE_MASK;
if (dev->dma_coherent || !iova)
if (dev->dma_coherent || WARN(handle == DMA_MAPPING_ERROR, "invalid iommu iova address.\n"))
return;
page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
@@ -1543,6 +1543,11 @@ static const struct dma_map_ops iommu_ops = {
.unmap_resource = arm_iommu_unmap_resource,
};
#ifdef CONFIG_ARCH_ROCKCHIP
#define RK_DMA_IOMMU_IOVA_BLOCK_SIZE SZ_2G
#define RK_DMA_IOMMU_BITMAP_SIZE ((RK_DMA_IOMMU_IOVA_BLOCK_SIZE >> PAGE_SHIFT) >> 3)
#endif
/**
* arm_iommu_create_mapping
* @bus: pointer to the bus holding the client device (for IOMMU calls)
@@ -1572,10 +1577,17 @@ arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size)
if (!bitmap_size)
return ERR_PTR(-EINVAL);
#ifdef RK_DMA_IOMMU_BITMAP_SIZE
if (bitmap_size > RK_DMA_IOMMU_BITMAP_SIZE) {
extensions = bitmap_size / RK_DMA_IOMMU_BITMAP_SIZE;
bitmap_size = RK_DMA_IOMMU_BITMAP_SIZE;
}
#else
if (bitmap_size > PAGE_SIZE) {
extensions = bitmap_size / PAGE_SIZE;
bitmap_size = PAGE_SIZE;
}
#endif
mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
if (!mapping)

1
arch/arm64/boot/dts/rockchip/Makefile
View File

@@ -294,6 +294,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-test5-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v20.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v20-amp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v20-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576s-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576s-evb1-v10-linux.dtb

78
arch/arm64/boot/dts/rockchip/rk3576-vehicle-amp.dtsi Normal file
View File

@@ -0,0 +1,78 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/soc/rockchip-amp.h>
#define CPU_GET_AFFINITY(cpuId, clusterId) (((cpuId) << 0) | ((clusterId) << 8))
/ {
rockchip_amp: rockchip-amp {
compatible = "rockchip,amp";
clocks = <&cru FCLK_BUS_CM0_CORE>, <&cru CLK_BUS_CM0_RTC>,
<&cru FCLK_PMU_CM0_CORE>, <&cru CLK_PMU_CM0_RTC>,
<&cru PCLK_MAILBOX0>,
<&cru SCLK_UART8>, <&cru PCLK_UART8>,
<&cru PCLK_BUSTIMER1>, <&cru CLK_TIMER10>, <&cru CLK_TIMER11>;
pinctrl-names = "default";
pinctrl-0 = <&uart8m1_xfer>;
amp-cpu-aff-maskbits = /bits/ 64 <0x0 0x1 0x1 0x2 0x2 0x4 0x3 0x8 0x100 0x10
0x101 0x20 0x102 0x40 0x103 0x80>;
amp-irqs = /bits/ 64 <GIC_AMP_IRQ_CFG_ROUTE(113, 0xd0, CPU_GET_AFFINITY(3, 0))
GIC_AMP_IRQ_CFG_ROUTE(174, 0xd0, CPU_GET_AFFINITY(3, 0))>;
status = "okay";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
mcu_reserved: mcu@47800000 {
reg = <0x0 0x47800000 0x0 0x100000>;
no-map;
};
amp_shmem_reserved: amp-shmem@47900000 {
reg = <0x0 0x47900000 0x0 0x400000>;
no-map;
};
rpmsg_reserved: rpmsg@47d00000 {
reg = <0x0 0x47d00000 0x0 0x200000>;
no-map;
};
rpmsg_dma_reserved: rpmsg-dma@47f00000 {
compatible = "shared-dma-pool";
reg = <0x0 0x47f00000 0x0 0x200000>;
no-map;
};
};
rpmsg: rpmsg@47d00000 {
compatible = "rockchip,rpmsg";
mbox-names = "rpmsg-rx", "rpmsg-tx";
mboxes = <&mailbox0 0 &mailbox3 0>;
rockchip,vdev-nums = <1>;
/* CPU3: link-id 0x03; MCU: link-id 0x04; */
rockchip,link-id = <0x03>;
reg = <0x0 0x47d00000 0x0 0x20000>;
memory-region = <&rpmsg_dma_reserved>;
status = "okay";
};
};
&mailbox0 {
rockchip,txpoll-period-ms = <1>;
status = "okay";
};
&mailbox3 {
rockchip,txpoll-period-ms = <1>;
status = "okay";
};

12
arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-amp.dts Normal file
View File

@@ -0,0 +1,12 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3576-vehicle-evb-v20.dts"
#include "rk3576-vehicle-amp.dtsi"
&uart8 {
status = "disabled";
};

4
arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dts
View File

@@ -320,8 +320,10 @@
compatible = "ethernet-phy-id0680.8101", "ethernet-phy-ieee802.3-c22";
reg = <2>;
clocks = <&cru CLK_MACPHY>;
clock-frequency = <24000000>;
clock-frequency = <50000000>;
resets = <&cru SRST_RESETN_MACPHY>;
pinctrl-names = "default";
pinctrl-0 = <&fephym2_pins>;
phy-is-integrated;
};
};

4
arch/arm64/boot/dts/rockchip/rv1126b.dtsi
View File

@@ -2382,9 +2382,9 @@
reg = <0x21280000 0x1000>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_RTC_ROOT>;
clocks = <&cru PCLK_RTC_TEST>;
clock-names = "pclk_phy";
assigned-clocks = <&cru PCLK_RTC_ROOT>;
assigned-clocks = <&cru PCLK_RTC_TEST>;
assigned-clock-rates = <50000000>;
status = "disabled";
};

160
arch/arm64/configs/rk3576_vehicle_amp.config Normal file
View File

@@ -0,0 +1,160 @@
CONFIG_AHCI_DWC=m
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_CW2017 is not set
# CONFIG_BATTERY_CW221X is not set
# CONFIG_BATTERY_RK817 is not set
# CONFIG_BATTERY_RK818 is not set
# CONFIG_CHARGER_BQ25700 is not set
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_RK817 is not set
# CONFIG_CHARGER_RK818 is not set
# CONFIG_CHARGER_SC8551 is not set
# CONFIG_CHARGER_SC89890 is not set
# CONFIG_CHARGER_SGM41542 is not set
# CONFIG_COMMON_CLK_PWM is not set
# CONFIG_COMPASS_DEVICE is not set
# CONFIG_CPU_IDLE_GOV_MENU is not set
CONFIG_CPU_IDLE_GOV_TEO=y
# CONFIG_CPU_PX30 is not set
# CONFIG_CPU_RK3328 is not set
# CONFIG_CPU_RK3368 is not set
# CONFIG_CPU_RK3399 is not set
# CONFIG_CPU_RK3528 is not set
# CONFIG_CPU_RK3562 is not set
# CONFIG_CPU_RK3568 is not set
# CONFIG_CRYPTO_DEV_ROCKCHIP_V1 is not set
# CONFIG_CRYPTO_DEV_ROCKCHIP_V3 is not set
# CONFIG_DRM_MAXIM_MAX96745 is not set
# CONFIG_DRM_MAXIM_MAX96755F is not set
# CONFIG_DRM_RK1000_TVE is not set
# CONFIG_DRM_RK630_TVE is not set
# CONFIG_DRM_ROHM_BU18XL82 is not set
# CONFIG_DRM_SII902X is not set
CONFIG_GPIO_NCA9539=y
# CONFIG_HALL_DEVICE is not set
CONFIG_HZ=1000
CONFIG_HZ_1000=y
# CONFIG_HZ_300 is not set
# CONFIG_IIO_ST_LSM6DSR is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_LIGHT_DEVICE is not set
CONFIG_LOG_BUF_SHIFT=20
# CONFIG_MALI400 is not set
# CONFIG_MALI_MIDGARD is not set
# CONFIG_MFD_RK618 is not set
# CONFIG_MFD_RK630_I2C is not set
# CONFIG_MFD_RKX110_X120 is not set
CONFIG_MFD_SERDES_DISPLAY=y
# CONFIG_PROXIMITY_DEVICE is not set
# CONFIG_R8168 is not set
CONFIG_REALTEK_PHY=y
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_FAN53555 is not set
# CONFIG_REGULATOR_LP8752 is not set
# CONFIG_REGULATOR_MP8865 is not set
# CONFIG_REGULATOR_TPS65132 is not set
# CONFIG_REGULATOR_WL2868C is not set
# CONFIG_REGULATOR_XZ3216 is not set
# CONFIG_ROCKCHIP_CHARGER_MANAGER is not set
# CONFIG_ROCKCHIP_CLK_BOOST is not set
# CONFIG_ROCKCHIP_CLK_INV is not set
# CONFIG_ROCKCHIP_CLK_PVTM is not set
# CONFIG_ROCKCHIP_DDRCLK_SIP is not set
# CONFIG_ROCKCHIP_DDRCLK_SIP_V2 is not set
CONFIG_ROCKCHIP_DRM_DIRECT_SHOW=y
# CONFIG_ROCKCHIP_PLL_RK3066 is not set
# CONFIG_ROCKCHIP_PLL_RK3399 is not set
# CONFIG_ROCKCHIP_SERDES_DRM_PANEL is not set
CONFIG_RTC_DRV_S35390A=y
# CONFIG_SLUB_SYSFS is not set
# CONFIG_SND_SOC_AW883XX is not set
# CONFIG_SND_SOC_CX2072X is not set
# CONFIG_SND_SOC_ES8311 is not set
# CONFIG_SND_SOC_ES8316 is not set
# CONFIG_SND_SOC_ES8326 is not set
# CONFIG_SND_SOC_ES8396 is not set
# CONFIG_SND_SOC_RK3328 is not set
# CONFIG_SND_SOC_RK3528 is not set
# CONFIG_SND_SOC_RK817 is not set
# CONFIG_SND_SOC_RK_CODEC_DIGITAL is not set
# CONFIG_SND_SOC_RT5640 is not set
# CONFIG_TOUCHSCREEN_ELAN5515 is not set
# CONFIG_TOUCHSCREEN_GSL3673 is not set
# CONFIG_TOUCHSCREEN_GSLX680_PAD is not set
CONFIG_TOUCHSCREEN_GT1X=m
CONFIG_TOUCHSCREEN_ILI210X=m
# CONFIG_UCS12CM0 is not set
# CONFIG_USB_ALI_M5632 is not set
# CONFIG_USB_AN2720 is not set
# CONFIG_USB_EPSON2888 is not set
# CONFIG_USB_HIDDEV is not set
# CONFIG_USB_KC2190 is not set
# CONFIG_USB_NET_CX82310_ETH is not set
# CONFIG_USB_NET_DM9601 is not set
# CONFIG_USB_NET_GL620A is not set
# CONFIG_USB_NET_INT51X1 is not set
# CONFIG_USB_NET_MCS7830 is not set
# CONFIG_USB_NET_SMSC75XX is not set
# CONFIG_USB_NET_SMSC95XX is not set
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_OHCI_HCD_PLATFORM=m
# CONFIG_VIDEO_AW36518 is not set
# CONFIG_VIDEO_AW8601 is not set
# CONFIG_VIDEO_CN3927V is not set
# CONFIG_VIDEO_DW9714 is not set
# CONFIG_VIDEO_FP5510 is not set
# CONFIG_VIDEO_GC2145 is not set
# CONFIG_VIDEO_GC2385 is not set
# CONFIG_VIDEO_GC4C33 is not set
# CONFIG_VIDEO_GC8034 is not set
# CONFIG_VIDEO_IMX415 is not set
CONFIG_VIDEO_MAXIM_SERDES=y
# CONFIG_VIDEO_OV02B10 is not set
# CONFIG_VIDEO_OV13850 is not set
# CONFIG_VIDEO_OV13855 is not set
# CONFIG_VIDEO_OV50C40 is not set
# CONFIG_VIDEO_OV5695 is not set
# CONFIG_VIDEO_OV8858 is not set
# CONFIG_VIDEO_RK628_BT1120 is not set
# CONFIG_VIDEO_RK628_CSI is not set
# CONFIG_VIDEO_RK_IRCUT is not set
# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V1X is not set
# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V21 is not set
# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32 is not set
# CONFIG_VIDEO_S5K3L6XX is not set
# CONFIG_VIDEO_S5KJN1 is not set
# CONFIG_VIDEO_SGM3784 is not set
# CONFIG_VL6180 is not set
# CONFIG_ROCKCHIP_DRM_SELF_TEST is not set
CONFIG_SERDES_DISPLAY_CHIP_MAXIM=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96745=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96752=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96755=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96772=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96789=y
CONFIG_SERDES_DISPLAY_CHIP_NOVO=y
CONFIG_SERDES_DISPLAY_CHIP_NOVO_NCA9539=y
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP=y
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP_RKX111=y
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP_RKX121=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18RL82=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18TL82=y
CONFIG_VIDEO_MAXIM_CAM_DUMMY=y
CONFIG_VIDEO_MAXIM_CAM_OV231X=y
CONFIG_VIDEO_MAXIM_CAM_OX01F10=y
CONFIG_VIDEO_MAXIM_CAM_OX03J10=y
CONFIG_VIDEO_MAXIM_CAM_SC320AT=y
# CONFIG_VIDEO_MAXIM_DES_MAXIM2C is not set
CONFIG_VIDEO_MAXIM_DES_MAXIM4C=y
CONFIG_VIDEO_MAXIM_SER_MAX9295=y
CONFIG_VIDEO_MAXIM_SER_MAX96715=y
CONFIG_VIDEO_MAXIM_SER_MAX96717=y
# CONFIG_VIDEO_REVERSE_IMAGE is not set
CONFIG_ROCKCHIP_AMP=y
CONFIG_MAILBOX=y
CONFIG_ROCKCHIP_MBOX=y
CONFIG_RPMSG_ROCKCHIP_MBOX=y
CONFIG_RPMSG_VIRTIO=y
CONFIG_RPMSG_CHAR=y
CONFIG_RPMSG_CTRL=y

2
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
View File

@@ -1040,7 +1040,7 @@
#define RV1126_GRF_IOFUNC_CON3 0x1026c
#define RV1126B_DSP_CTRL1 0x0024
#define RV1126B_CLK_CNT 0x0040
#define RV1126B_CLK_CNT 0x0044
#define RV1126B_GRF_VOP_LCDC_CON 0x30b9c
#define RV1126B_WB_CTRL 0x0280
#define RV1126B_WB_XSCAL_FACTOR 0x0284

10
drivers/media/i2c/Kconfig
View File

@@ -2078,6 +2078,16 @@ config VIDEO_SC5336
This is a Video4Linux2 sensor driver for the SmartSens
SC5336 camera.
config VIDEO_SC635HAI
tristate "SmartSens SC635HAI sensor support"
depends on I2C && VIDEO_DEV
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
This is a Video4Linux2 sensor driver for the SmartSens
SC635HAI camera.
config VIDEO_SC830AI
tristate "SmartSens SC830AI sensor support"
depends on I2C && VIDEO_DEV

1
drivers/media/i2c/Makefile
View File

@@ -256,6 +256,7 @@ obj-$(CONFIG_VIDEO_SC500AI) += sc500ai.o
obj-$(CONFIG_VIDEO_SC501AI) += sc501ai.o
obj-$(CONFIG_VIDEO_SC530AI) += sc530ai.o
obj-$(CONFIG_VIDEO_SC5336) += sc5336.o
obj-$(CONFIG_VIDEO_SC635HAI) += sc635hai.o
obj-$(CONFIG_VIDEO_SC830AI) += sc830ai.o
obj-$(CONFIG_VIDEO_SC831AI) += sc831ai.o
obj-$(CONFIG_VIDEO_SC850SL) += sc850sl.o

243
drivers/media/i2c/lt6911uxe.c
View File

@@ -14,6 +14,7 @@
* 1.fix some errors.
* 2.add dphy timing reg.
* V0.0X01.0X05 add dual mipi mode support
* V0.0X01.0X06 add yuv420 8bit
*
*/
// #define DEBUG
@@ -41,7 +42,7 @@
#include <media/v4l2-event.h>
#include <media/v4l2-fwnode.h>
#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x06)
static int debug;
module_param(debug, int, 0644);
@@ -51,14 +52,19 @@ MODULE_PARM_DESC(debug, "debug level (0-3)");
#define POLL_INTERVAL_MS 1000
#define LT6911UXE_LINK_FREQ_1250M 1250000000
#define LT6911UXE_LINK_FREQ_1100M 1100000000
#define LT6911UXE_LINK_FREQ_1000M 1000000000
#define LT6911UXE_LINK_FREQ_900M 900000000
#define LT6911UXE_LINK_FREQ_800M 800000000
#define LT6911UXE_LINK_FREQ_700M 700000000
#define LT6911UXE_LINK_FREQ_600M 600000000
#define LT6911UXE_LINK_FREQ_450M 450000000
#define LT6911UXE_LINK_FREQ_500M 500000000
#define LT6911UXE_LINK_FREQ_400M 400000000
#define LT6911UXE_LINK_FREQ_300M 300000000
#define LT6911UXE_LINK_FREQ_200M 200000000
#define LT6911UXE_LINK_FREQ_150M 150000000
#define LT6911UXE_LINK_FREQ_100M 100000000
#define LT6911UXE_LINK_FREQ_50M 50000000
#define LT6911UXE_PIXEL_RATE 800000000
#define LT6911UXE_CHIPID 0x0221
@@ -131,34 +137,57 @@ MODULE_PARM_DESC(debug, "debug level (0-3)");
#define MIPI_TX_PT0_LPTX 0xe234
#define MIPI_TX_PT1_LPTX 0xe244
// #define LT6911UXE_OUT_RGB
#ifdef LT6911UXE_OUT_RGB
#define LT6911UXE_MEDIA_BUS_FMT MEDIA_BUS_FMT_BGR888_1X24
#else
#define LT6911UXE_MEDIA_BUS_FMT MEDIA_BUS_FMT_UYVY8_2X8
#endif
enum lt6911uxe_bus_fmt {
RGB_6Bit = 0,
RGB_8Bit,
RGB_10Bit,
RGB_12Bit,
YUV444_8Bit,
YUV444_10Bit,
YUV444_12Bit,
YUV422_8Bit,
YUV422_10Bit,
YUV422_12Bit,
YUV420_8Bit,
YUV420_10Bit,
YUV420_12Bit,
};
static const char * const bus_format_str[] = {
"RGB_6Bit",
"RGB_8Bit",
"RGB_10Bit",
"RGB_12Bit",
"YUV444_8Bit",
"YUV444_10Bit",
"YUV444_12Bit",
"YUV422_8Bit",
"YUV422_10Bit",
"YUV422_12Bit",
"YUV420_8Bit",
"YUV420_10Bit",
"YUV420_12Bit",
"UNKNOWN",
};
#define LT6911UXE_NAME "LT6911UXE"
#ifdef LT6911UXE_OUT_RGB
static const s64 link_freq_menu_items[] = {
LT6911UXE_LINK_FREQ_1250M,
LT6911UXE_LINK_FREQ_1100M,
LT6911UXE_LINK_FREQ_1000M,
LT6911UXE_LINK_FREQ_900M,
LT6911UXE_LINK_FREQ_800M,
LT6911UXE_LINK_FREQ_700M,
LT6911UXE_LINK_FREQ_600M,
LT6911UXE_LINK_FREQ_450M,
LT6911UXE_LINK_FREQ_300M,
LT6911UXE_LINK_FREQ_150M,
};
#else
static const s64 link_freq_menu_items[] = {
LT6911UXE_LINK_FREQ_1250M,
LT6911UXE_LINK_FREQ_600M,
LT6911UXE_LINK_FREQ_500M,
LT6911UXE_LINK_FREQ_400M,
LT6911UXE_LINK_FREQ_300M,
LT6911UXE_LINK_FREQ_200M,
LT6911UXE_LINK_FREQ_150M,
LT6911UXE_LINK_FREQ_100M,
LT6911UXE_LINK_FREQ_50M,
};
#endif
struct lt6911uxe {
struct v4l2_mbus_config_mipi_csi2 bus;
@@ -200,6 +229,9 @@ struct lt6911uxe {
u32 audio_sampling_rate;
int lane_in_use;
bool dual_mipi_port;
u8 bus_fmt;
bool rgb_out;
u32 cur_fps;
};
static const struct v4l2_dv_timings_cap lt6911uxe_timings_cap = {
@@ -788,7 +820,7 @@ static int lt6911uxe_get_detected_timings(struct v4l2_subdev *sd,
struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
struct v4l2_bt_timings *bt = &timings->bt;
u32 hact, vact, htotal, vtotal, hs, vs, hbp, vbp, hfp, vfp;
u32 pixel_clock, fps, halt_pix_clk;
u32 pixel_clock, halt_pix_clk;
u8 clk_h, clk_m, clk_l;
u8 val_h, val_l;
u32 byte_clk, mipi_clk, mipi_data_rate;
@@ -839,6 +871,15 @@ static int lt6911uxe_get_detected_timings(struct v4l2_subdev *sd,
vbp = vtotal - vact - vs - vfp;
lt6911uxe->bus_fmt = i2c_rd8(sd, BUS_FMT);
if (lt6911uxe->bus_fmt == YUV420_8Bit) {
hact *= 2;
hs *= 2;
hfp *= 2;
hbp *= 2;
htotal *= 2;
pixel_clock *= 2;
}
lt6911uxe->nosignal = false;
lt6911uxe->is_audio_present = true;
timings->type = V4L2_DV_BT_656_1120;
@@ -852,7 +893,7 @@ static int lt6911uxe_get_detected_timings(struct v4l2_subdev *sd,
bt->hbackporch = hbp;
bt->vbackporch = vbp;
bt->pixelclock = pixel_clock;
fps = pixel_clock / (htotal * vtotal);
lt6911uxe->cur_fps = pixel_clock / (htotal * vtotal);
/* for interlaced res 1080i 576i 480i*/
if ((hact == 1920 && vact == 540) || (hact == 1440 && vact == 288)
@@ -864,14 +905,23 @@ static int lt6911uxe_get_detected_timings(struct v4l2_subdev *sd,
bt->interlaced = V4L2_DV_PROGRESSIVE;
}
if (!lt6911uxe_rcv_supported_res(sd, hact, bt->height)) {
lt6911uxe->nosignal = true;
v4l2_err(sd, "%s: rcv err res, return no signal!\n", __func__);
return -EINVAL;
if (lt6911uxe->bus_fmt == YUV420_8Bit) {
lt6911uxe->mbus_fmt_code = MEDIA_BUS_FMT_UV8_1X8;
} else {
if (lt6911uxe->rgb_out)
lt6911uxe->mbus_fmt_code = MEDIA_BUS_FMT_BGR888_1X24;
else
lt6911uxe->mbus_fmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
}
v4l2_info(sd, "act:%dx%d, total:%dx%d, pixclk:%d, fps:%d\n",
hact, vact, htotal, vtotal, pixel_clock, fps);
if (!lt6911uxe_rcv_supported_res(sd, bt->width, bt->height)) {
lt6911uxe->nosignal = true;
v4l2_err(sd, "%s: rcv err res, return no signal!\n", __func__);
}
v4l2_info(sd, "act:%dx%d, total:%dx%d, pixclk:%u, fps:%d, bus fmt:%s\n",
hact, vact, htotal, vtotal, pixel_clock,
lt6911uxe->cur_fps, bus_format_str[lt6911uxe->bus_fmt]);
v4l2_info(sd, "byte_clk:%u, mipi_clk:%u, mipi_data_rate:%u\n",
byte_clk, mipi_clk, mipi_data_rate);
v4l2_info(sd, "hfp:%d, hs:%d, hbp:%d, vfp:%d, vs:%d, vbp:%d, inerlaced:%d\n",
@@ -936,42 +986,14 @@ static int lt6911uxe_update_controls(struct v4l2_subdev *sd)
return ret;
}
static void lt6911uxe_config_dphy_timing(struct v4l2_subdev *sd)
{
u8 val;
val = i2c_rd8(sd, CLK_ZERO_REG);
i2c_wr8(sd, CLK_ZERO_REG, val);
val = i2c_rd8(sd, HS_PREPARE_REG);
i2c_wr8(sd, HS_PREPARE_REG, val);
val = i2c_rd8(sd, HS_TRAIL);
i2c_wr8(sd, HS_TRAIL, val);
v4l2_info(sd, "%s: dphy timing: hs trail = %x\n", __func__, val);
val = i2c_rd8(sd, MIPI_TX_PT0_TX0_DLY);
i2c_wr8_and_or(sd, MIPI_TX_PT0_TX0_DLY, ~MIPI_TIMING_MASK, val);
v4l2_info(sd, "%s: dphy timing: port0 tx0 delay = %x\n", __func__, val);
val = i2c_rd8(sd, MIPI_TX_PT0_LPTX);
i2c_wr8(sd, MIPI_TX_PT0_LPTX, val);
v4l2_info(sd, "%s: dphy timing: port0 lptx = %x\n", __func__, val);
v4l2_info(sd, "%s: dphy timing config done.\n", __func__);
}
static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
{
struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
if (enable) {
lt6911uxe_config_dphy_timing(sd);
usleep_range(5000, 6000);
if (enable)
i2c_wr8(&lt6911uxe->sd, STREAM_CTL, ENABLE_STREAM);
} else {
else
i2c_wr8(&lt6911uxe->sd, STREAM_CTL, DISABLE_STREAM);
}
msleep(20);
v4l2_dbg(2, debug, sd, "%s: %sable\n",
@@ -1170,11 +1192,8 @@ static int lt6911uxe_s_stream(struct v4l2_subdev *sd, int on)
struct i2c_client *client = lt6911uxe->i2c_client;
dev_info(&client->dev, "%s: on: %d, %dx%d%s%d\n", __func__, on,
lt6911uxe->cur_mode->width,
lt6911uxe->cur_mode->height,
lt6911uxe->cur_mode->interlace ? "I" : "P",
DIV_ROUND_CLOSEST(lt6911uxe->cur_mode->max_fps.denominator,
lt6911uxe->cur_mode->max_fps.numerator));
lt6911uxe->timings.bt.width, lt6911uxe->timings.bt.height,
lt6911uxe->timings.bt.interlaced ? "I" : "P", lt6911uxe->cur_fps);
enable_stream(sd, on);
return 0;
@@ -1184,9 +1203,11 @@ static int lt6911uxe_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_mbus_code_enum *code)
{
struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
switch (code->index) {
case 0:
code->code = LT6911UXE_MEDIA_BUS_FMT;
code->code = lt6911uxe->mbus_fmt_code;
break;
default:
@@ -1205,7 +1226,7 @@ static int lt6911uxe_enum_frame_sizes(struct v4l2_subdev *sd,
if (fse->index >= lt6911uxe->cfg_num)
return -EINVAL;
if (fse->code != LT6911UXE_MEDIA_BUS_FMT)
if (fse->code != lt6911uxe->mbus_fmt_code)
return -EINVAL;
fse->min_width = lt6911uxe->support_modes[fse->index].width;
@@ -1225,7 +1246,7 @@ static int lt6911uxe_enum_frame_interval(struct v4l2_subdev *sd,
if (fie->index >= lt6911uxe->cfg_num)
return -EINVAL;
fie->code = LT6911UXE_MEDIA_BUS_FMT;
fie->code = lt6911uxe->mbus_fmt_code;
fie->width = lt6911uxe->support_modes[fie->index].width;
fie->height = lt6911uxe->support_modes[fie->index].height;
@@ -1276,12 +1297,69 @@ lt6911uxe_find_best_fit(struct lt6911uxe *lt6911uxe)
return &lt6911uxe->support_modes[cur_best_fit];
}
static int lt6911uxe_get_format_bpp(struct v4l2_subdev *sd)
{
struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
u32 code = lt6911uxe->mbus_fmt_code;
switch (code) {
case MEDIA_BUS_FMT_UYVY8_2X8:
return 16;
case MEDIA_BUS_FMT_BGR888_1X24:
return 24;
case MEDIA_BUS_FMT_UV8_1X8:
return 12;
default:
return 16;
}
}
static u64 lt6911uxe_get_lane_rate_bps(struct v4l2_subdev *sd)
{
struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
u64 lane_rate;
u64 max_lane_rate = 2500000000U;
u8 bpp;
u64 pixelclock = lt6911uxe->timings.bt.pixelclock;
u32 lanes = lt6911uxe->bus_cfg.bus.mipi_csi2.num_data_lanes;
bpp = lt6911uxe_get_format_bpp(sd);
lane_rate = pixelclock * bpp;
lane_rate = div_u64(lane_rate, lanes);
lane_rate = DIV_ROUND_UP(lane_rate * 10, 9);
if (lane_rate > max_lane_rate)
lane_rate = max_lane_rate;
return lane_rate;
}
static int lt6911uxe_get_mipi_freq_idx(struct v4l2_subdev *sd)
{
u64 mipi_freq;
u64 dist;
u64 cur_best_idx = 0;
u64 cur_dist;
unsigned int i;
mipi_freq = lt6911uxe_get_lane_rate_bps(sd) / 2;
dist = abs(mipi_freq - link_freq_menu_items[0]);
for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
cur_dist = abs(mipi_freq - link_freq_menu_items[i]);
if (cur_dist < dist) {
dist = cur_dist;
cur_best_idx = i;
}
}
return cur_best_idx;
}
static int lt6911uxe_get_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *format)
{
struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
const struct lt6911uxe_mode *mode;
int mipi_freq_idx;
mutex_lock(&lt6911uxe->confctl_mutex);
format->format.code = lt6911uxe->mbus_fmt_code;
@@ -1293,15 +1371,14 @@ static int lt6911uxe_get_fmt(struct v4l2_subdev *sd,
format->format.colorspace = V4L2_COLORSPACE_SRGB;
mutex_unlock(&lt6911uxe->confctl_mutex);
mode = lt6911uxe_find_best_fit(lt6911uxe);
lt6911uxe->cur_mode = mode;
mipi_freq_idx = lt6911uxe_get_mipi_freq_idx(sd);
__v4l2_ctrl_s_ctrl_int64(lt6911uxe->pixel_rate,
LT6911UXE_PIXEL_RATE);
__v4l2_ctrl_s_ctrl(lt6911uxe->link_freq,
mode->mipi_freq_idx);
mipi_freq_idx);
v4l2_dbg(1, debug, sd, "%s: mode->mipi_freq_idx(%d)", __func__, mode->mipi_freq_idx);
v4l2_dbg(1, debug, sd, "%s: mipi_freq_idx(%d)", __func__, mipi_freq_idx);
v4l2_dbg(1, debug, sd, "%s: fmt code:%d, w:%d, h:%d, field code:%d\n",
__func__, format->format.code, format->format.width,
@@ -1327,9 +1404,18 @@ static int lt6911uxe_set_fmt(struct v4l2_subdev *sd,
return ret;
switch (code) {
case LT6911UXE_MEDIA_BUS_FMT:
break;
case MEDIA_BUS_FMT_UYVY8_2X8:
if (lt6911uxe->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_2X8)
break;
return -EINVAL;
case MEDIA_BUS_FMT_BGR888_1X24:
if (lt6911uxe->mbus_fmt_code == MEDIA_BUS_FMT_BGR888_1X24)
break;
return -EINVAL;
case MEDIA_BUS_FMT_UV8_1X8:
if (lt6911uxe->mbus_fmt_code == MEDIA_BUS_FMT_UV8_1X8)
break;
return -EINVAL;
default:
return -EINVAL;
}
@@ -1542,7 +1628,7 @@ static int lt6911uxe_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
/* Initialize try_fmt */
try_fmt->width = def_mode->width;
try_fmt->height = def_mode->height;
try_fmt->code = LT6911UXE_MEDIA_BUS_FMT;
try_fmt->code = lt6911uxe->mbus_fmt_code;
try_fmt->field = V4L2_FIELD_NONE;
mutex_unlock(&lt6911uxe->confctl_mutex);
@@ -1719,6 +1805,9 @@ static int lt6911uxe_probe_of(struct lt6911uxe *lt6911uxe)
return ret;
}
if (of_property_read_bool(dev->of_node, "output-rgb"))
lt6911uxe->rgb_out = true;
ep = of_graph_get_next_endpoint(dev->of_node, NULL);
if (!ep) {
dev_err(dev, "missing endpoint node\n");
@@ -1844,7 +1933,6 @@ static int lt6911uxe_probe(struct i2c_client *client,
sd = &lt6911uxe->sd;
lt6911uxe->i2c_client = client;
lt6911uxe->mbus_fmt_code = LT6911UXE_MEDIA_BUS_FMT;
err = lt6911uxe_probe_of(lt6911uxe);
if (err) {
@@ -1854,6 +1942,10 @@ static int lt6911uxe_probe(struct i2c_client *client,
lt6911uxe->timings = default_timing;
lt6911uxe->cur_mode = &lt6911uxe->support_modes[0];
if (lt6911uxe->rgb_out)
lt6911uxe->mbus_fmt_code = MEDIA_BUS_FMT_BGR888_1X24;
else
lt6911uxe->mbus_fmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
err = lt6911uxe_get_multi_dev_info(lt6911uxe);
if (err)
@@ -1940,7 +2032,8 @@ static int lt6911uxe_probe(struct i2c_client *client,
v4l2_err(sd, "v4l2 ctrl handler setup failed! err:%d\n", err);
goto err_work_queues;
}
enable_stream(sd, false);
schedule_delayed_work(&lt6911uxe->delayed_work_res_change, msecs_to_jiffies(50));
v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
client->addr << 1, client->adapter->name);

945
drivers/media/i2c/sc450ai.c
View File

File diff suppressed because it is too large Load Diff

2975
drivers/media/i2c/sc635hai.c Normal file
View File

File diff suppressed because it is too large Load Diff

11
drivers/media/platform/rockchip/aiisp/aiisp.c
View File

@@ -1112,7 +1112,7 @@ static int rkaiisp_update_buf(struct rkaiisp_device *aidev)
struct rkaiisp_hw_dev *hw_dev = aidev->hw_dev;
struct rkisp_aiisp_st idxbuf = {0};
unsigned long flags = 0;
int ret = -1;
int ret = 0;
spin_lock_irqsave(&hw_dev->hw_lock, flags);
if (!kfifo_is_empty(fifo))
@@ -1497,6 +1497,9 @@ static void rkaiisp_vb2_buf_queue(struct vb2_buffer *vb)
spin_lock_irqsave(&aidev->config_lock, flags);
list_add_tail(&buf->queue, &aidev->params);
spin_unlock_irqrestore(&aidev->config_lock, flags);
v4l2_dbg(1, rkaiisp_debug, &aidev->v4l2_dev,
"queue param buffer\n");
}
static void rkaiisp_vb2_stop_streaming(struct vb2_queue *vq)
@@ -1544,6 +1547,9 @@ static void rkaiisp_vb2_stop_streaming(struct vb2_queue *vq)
pm_runtime_put_sync(aidev->dev);
atomic_dec(&hw_dev->refcnt);
v4l2_dbg(1, rkaiisp_debug, &aidev->v4l2_dev,
"stop streaming %d, hwstate %d\n", aidev->streamon, aidev->hwstate);
}
static int
@@ -1561,6 +1567,9 @@ rkaiisp_vb2_start_streaming(struct vb2_queue *queue, unsigned int count)
pm_runtime_get_sync(aidev->dev);
atomic_inc(&hw_dev->refcnt);
v4l2_dbg(1, rkaiisp_debug, &aidev->v4l2_dev,
"start streaming %d\n", aidev->streamon);
return 0;
}

3
drivers/media/platform/rockchip/aiisp/hw.c
View File

@@ -68,10 +68,8 @@ static irqreturn_t hw_irq_hdl(int irq, void *ctx)
id = i;
}
}
spin_unlock(&hw_dev->hw_lock);
if (max > 0) {
spin_lock(&hw_dev->hw_lock);
hw_dev->is_idle = false;
hw_dev->cur_dev_id = id;
aidev = hw_dev->aidev[hw_dev->cur_dev_id];
@@ -81,7 +79,6 @@ static irqreturn_t hw_irq_hdl(int irq, void *ctx)
hw_dev->cur_dev_id, max);
rkaiisp_trigger(aidev);
} else {
spin_lock(&hw_dev->hw_lock);
hw_dev->is_idle = true;
spin_unlock(&hw_dev->hw_lock);
}

8
drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c
View File

@@ -715,10 +715,10 @@ static void hdmirx_get_colordepth(struct rk_hdmirx_dev *hdmirx_dev)
__func__, hdmirx_dev->color_depth, color_depth_reg);
}
static void hdmirx_get_pix_fmt(struct rk_hdmirx_dev *hdmirx_dev)
static void hdmirx_get_pix_fmt(struct rk_hdmirx_dev *hdmirx_dev, bool retry)
{
u32 val;
int timeout = 10;
int timeout = retry ? 10 : 0;
struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
try_loop:
@@ -1009,7 +1009,7 @@ static int hdmirx_get_detected_timings(struct rk_hdmirx_dev *hdmirx_dev,
val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);
field_type = (val & HDMIRX_TYPE_MASK) >> 7;
hdmirx_get_pix_fmt(hdmirx_dev);
hdmirx_get_pix_fmt(hdmirx_dev, true);
hdmirx_get_color_range(hdmirx_dev);
hdmirx_get_color_space(hdmirx_dev);
bt->interlaced = field_type & BIT(0) ?
@@ -2830,7 +2830,7 @@ static void pkt_0_int_handler(struct rk_hdmirx_dev *hdmirx_dev,
if ((status & PKTDEC_AVIIF_CHG_IRQ)) {
hdmirx_get_color_range(hdmirx_dev);
hdmirx_get_color_space(hdmirx_dev);
hdmirx_get_pix_fmt(hdmirx_dev);
hdmirx_get_pix_fmt(hdmirx_dev, false);
if (hdmirx_dev->cur_fmt_fourcc != pre_fmt_fourcc ||
hdmirx_dev->cur_color_range != pre_color_range ||
hdmirx_dev->cur_color_space != pre_color_space) {

43
drivers/media/platform/rockchip/isp/capture_v35.c
View File

@@ -910,7 +910,7 @@ static int mi_frame_end(struct rkisp_stream *stream, u32 state)
struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
unsigned long lock_flags = 0;
struct rkisp_buffer *buf = NULL;
u32 i;
u32 i, seq;
/* STREAM_VIR or STREAM_MP wrap buf from rockit */
if (stream->id == RKISP_STREAM_VIR ||
@@ -955,22 +955,50 @@ static int mi_frame_end(struct rkisp_stream *stream, u32 state)
goto end;
}
rkisp_dmarx_get_frame(dev, &seq, NULL, &ns, !dev->is_aiisp_en);
if (!ns)
ns = rkisp_time_get_ns(dev);
for (i = 0; i < isp_fmt->mplanes; i++) {
u32 payload_size = stream->out_fmt.plane_fmt[i].sizeimage;
vb2_set_plane_payload(vb2_buf, i, payload_size);
if (stream->is_attach_info &&
vb2_buf->memory && i == isp_fmt->mplanes - 1) {
struct rkisp_frame_info *info = buf->vaddr[i] + payload_size;
struct sensor_exposure_cfg *exp = &dev->params_vdev.exposure;
info->seq = seq;
info->hdr = dev->params_vdev.is_hdr;
info->timestamp = IS_HDR_RDBK(dev->rd_mode) ? ns : dev->vicap_sof.timestamp;
info->rolling_shutter_skew = exp->linear_exp.rolling_shutter_skew;
info->sensor_exposure_time = exp->linear_exp.coarse_integration_time;
info->sensor_analog_gain = exp->linear_exp.analog_gain_code_global;
info->sensor_digital_gain = exp->linear_exp.digital_gain_global;
info->isp_digital_gain = exp->linear_exp.isp_digital_gain;
if (info->hdr) {
info->rolling_shutter_skew = exp->hdr_exp[0].rolling_shutter_skew;
info->sensor_exposure_time = exp->hdr_exp[0].coarse_integration_time;
info->sensor_analog_gain = exp->hdr_exp[0].analog_gain_code_global;
info->sensor_digital_gain = exp->hdr_exp[0].digital_gain_global;
info->isp_digital_gain = exp->hdr_exp[0].isp_digital_gain;
info->sensor_exposure_time_l = exp->hdr_exp[1].coarse_integration_time;
info->sensor_analog_gain_l = exp->hdr_exp[1].analog_gain_code_global;
info->sensor_digital_gain_l = exp->hdr_exp[1].digital_gain_global;
info->isp_digital_gain_l = exp->hdr_exp[1].isp_digital_gain;
}
}
}
rkisp_dmarx_get_frame(dev, &i, NULL, &ns, !dev->is_aiisp_en);
if (!ns)
ns = rkisp_time_get_ns(dev);
buf->vb.sequence = i;
buf->vb.sequence = seq;
vb2_buf->timestamp = ns;
ns = rkisp_time_get_ns(dev);
stream->dbg.interval = ns - stream->dbg.timestamp;
stream->dbg.delay = ns - vb2_buf->timestamp;
stream->dbg.timestamp = ns;
stream->dbg.id = i;
stream->dbg.id = seq;
if (vir->streaming && vir->conn_id == stream->id) {
spin_lock_irqsave(&vir->vbq_lock, lock_flags);
@@ -1120,6 +1148,9 @@ static int rkisp_queue_setup(struct vb2_queue *queue,
plane_fmt->sizeimage / height *
ALIGN(height, 16) :
plane_fmt->sizeimage;
/* attach information size */
if (stream->is_attach_info && i == isp_fmt->mplanes - 1)
sizes[i] += sizeof(struct rkisp_frame_info);
}
rkisp_chk_tb_over(dev);

2
drivers/media/platform/rockchip/isp/hw.c
View File

@@ -836,8 +836,6 @@ static const struct isp_clk_info rv1126b_isp_clk_rate[] = {
.clk_rate = 400,
}, {
.clk_rate = 500,
}, {
.clk_rate = 600,
}
};

31
drivers/media/platform/rockchip/isp/isp_params_v35.c
View File

@@ -535,7 +535,7 @@ isp_lsc_config(struct rkisp_isp_params_vdev *params_vdev,
}
ctrl = isp3_param_read(params_vdev, ISP3X_LSC_CTRL, id);
ctrl &= ISP35_MODULE_EN;
ctrl &= (ISP35_MODULE_EN | ISP3X_LSC_PRE_RD_ST_MODE);
ctrl |= !!arg->sector_16x16 << 2;
isp3_param_write(params_vdev, ctrl, ISP3X_LSC_CTRL, id);
@@ -547,15 +547,38 @@ isp_lsc_config(struct rkisp_isp_params_vdev *params_vdev,
static void
isp_lsc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
{
struct rkisp_device *dev = params_vdev->dev;
u32 val = isp3_param_read(params_vdev, ISP3X_LSC_CTRL, id);
u32 path_sel;
if (en == !!(val & ISP35_MODULE_EN))
return;
if (en)
if (en) {
val |= ISP35_MODULE_EN;
else
if (dev->is_aiisp_en && !dev->is_aiisp_sync) {
val &= ~ISP3X_LSC_PRE_RD_ST_MODE;
path_sel = isp3_param_read_cache(params_vdev, ISP3X_VI_ISP_PATH, id);
/* drcLSC default frame end read table */
path_sel |= ISP3X_LSC_CFG_SEL(3);
isp3_param_write(params_vdev, path_sel, ISP3X_VI_ISP_PATH, id);
isp3_param_write(params_vdev, val, ISP3X_LSC_CTRL, id);
/* awbLSC default frame end read table */
path_sel &= ~ISP3X_LSC_CFG_SEL(3);
path_sel |= ISP3X_LSC_CFG_SEL(2);
isp3_param_write(params_vdev, path_sel, ISP3X_VI_ISP_PATH, id);
isp3_param_write(params_vdev, val, ISP3X_LSC_CTRL, id);
/* mainLSC default frame start read table and change to frame end */
path_sel &= ~ISP3X_LSC_CFG_SEL(3);
path_sel |= ISP3X_LSC_CFG_SEL(1);
isp3_param_write(params_vdev, path_sel, ISP3X_VI_ISP_PATH, id);
val |= ISP3X_LSC_PRE_RD_ST_MODE;
}
} else {
val &= ~(ISP35_MODULE_EN | ISP35_SELF_FORCE_UPD);
}
isp3_param_write(params_vdev, val, ISP3X_LSC_CTRL, id);
}
@@ -1267,6 +1290,8 @@ isp_rawawb_config(struct rkisp_isp_params_vdev *params_vdev,
!!arg->blk_measure_xytype << 2 |
!!arg->blk_measure_mode << 1 |
!!arg->blk_measure_enable;
if (dev->is_aiisp_en)
value |= ISP35_RAWAWB_BNR_BE_SEL;
isp3_param_write(params_vdev, value, ISP3X_RAWAWB_BLK_CTRL, id);
h_offs = arg->h_offs & ~0x1;

26
drivers/media/platform/rockchip/isp/isp_rockit.c
View File

@@ -320,6 +320,32 @@ int rkisp_rockit_buf_done(struct rkisp_stream *stream, int cmd, struct rkisp_buf
ISP33_ISP2ENC_FRM_CNT(rkisp_read(dev, ISP3X_ISP_DEBUG1, true));
}
if (stream->is_attach_info) {
struct sensor_exposure_cfg *exp = &dev->params_vdev.exposure;
if (!IS_HDR_RDBK(dev->rd_mode))
rockit_cfg->frame.u64PTS = dev->vicap_sof.timestamp;
rockit_cfg->frame.hdr = dev->params_vdev.is_hdr;
rockit_cfg->frame.rolling_shutter_skew = exp->linear_exp.rolling_shutter_skew;
rockit_cfg->frame.sensor_exposure_time = exp->linear_exp.coarse_integration_time;
rockit_cfg->frame.sensor_analog_gain = exp->linear_exp.analog_gain_code_global;
rockit_cfg->frame.sensor_digital_gain = exp->linear_exp.digital_gain_global;
rockit_cfg->frame.isp_digital_gain = exp->linear_exp.isp_digital_gain;
if (rockit_cfg->frame.hdr) {
rockit_cfg->frame.rolling_shutter_skew = exp->hdr_exp[0].rolling_shutter_skew;
rockit_cfg->frame.sensor_exposure_time = exp->hdr_exp[0].coarse_integration_time;
rockit_cfg->frame.sensor_analog_gain = exp->hdr_exp[0].analog_gain_code_global;
rockit_cfg->frame.sensor_digital_gain = exp->hdr_exp[0].digital_gain_global;
rockit_cfg->frame.isp_digital_gain = exp->hdr_exp[0].isp_digital_gain;
rockit_cfg->frame.sensor_exposure_time_l = exp->hdr_exp[1].coarse_integration_time;
rockit_cfg->frame.sensor_analog_gain_l = exp->hdr_exp[1].analog_gain_code_global;
rockit_cfg->frame.sensor_digital_gain_l = exp->hdr_exp[1].digital_gain_global;
rockit_cfg->frame.isp_digital_gain_l = exp->hdr_exp[1].isp_digital_gain;
}
}
rockit_cfg->is_color = !rkisp_read(dev, ISP3X_IMG_EFF_CTRL, true);
rockit_cfg->frame.u32Height = stream->out_fmt.height;

2
drivers/media/platform/rockchip/isp/regs_v3x.h
View File

@@ -3358,6 +3358,8 @@
#define ISP32_RAWAWB_2DDR_PATH_DS BIT(27)
#define ISP32_RAWAWB_2DDR_PATH_ERR BIT(29)
#define ISP35_RAWAWB_BNR_BE_SEL BIT(10)
#define ISP33_RAWAWB_WRAM_CLR BIT(31)
/* AIAWB */

3
drivers/media/platform/rockchip/vpss/stream_v20.c
View File

@@ -1184,7 +1184,8 @@ static void rkvpss_frame_end(struct rkvpss_stream *stream)
vb2_set_plane_payload(vb2_buf, i, payload_size);
if (stream->is_attach_info && i == fmt->mplanes - 1) {
if (stream->is_attach_info &&
vb2_buf->memory && i == fmt->mplanes - 1) {
struct rkvpss_frame_info *dst_info = buf->vaddr[i] + payload_size;
struct rkisp_vpss_frame_info *src_info = &dev->frame_info;

23
drivers/media/platform/rockchip/vpss/vpss_rockit.c
View File

@@ -314,6 +314,29 @@ int rkvpss_rockit_buf_done(struct rkvpss_stream *stream, int cmd, struct rkvpss_
rockit_vpss_cfg->node = stream_cfg->node;
rockit_vpss_cfg->event = cmd;
if (stream->is_attach_info) {
struct rkisp_vpss_frame_info *src_info = &vpss_dev->frame_info;
rockit_vpss_cfg->frame.u64PTS = src_info->timestamp;
rockit_vpss_cfg->frame.hdr = src_info->hdr;
rockit_vpss_cfg->frame.rolling_shutter_skew = src_info->rolling_shutter_skew;
rockit_vpss_cfg->frame.sensor_exposure_time = src_info->sensor_exposure_time;
rockit_vpss_cfg->frame.sensor_analog_gain = src_info->sensor_analog_gain;
rockit_vpss_cfg->frame.sensor_digital_gain = src_info->sensor_digital_gain;
rockit_vpss_cfg->frame.isp_digital_gain = src_info->isp_digital_gain;
rockit_vpss_cfg->frame.sensor_exposure_time_m = src_info->sensor_exposure_time_m;
rockit_vpss_cfg->frame.sensor_analog_gain_m = src_info->sensor_analog_gain_m;
rockit_vpss_cfg->frame.sensor_digital_gain_m = src_info->sensor_digital_gain_m;
rockit_vpss_cfg->frame.isp_digital_gain_m = src_info->isp_digital_gain_m;
rockit_vpss_cfg->frame.sensor_exposure_time_l = src_info->sensor_exposure_time_l;
rockit_vpss_cfg->frame.sensor_analog_gain_l = src_info->sensor_analog_gain_l;
rockit_vpss_cfg->frame.sensor_digital_gain_l = src_info->sensor_digital_gain_l;
rockit_vpss_cfg->frame.isp_digital_gain_l = src_info->isp_digital_gain_l;
}
if (list_empty(&stream->buf_queue))
rockit_vpss_cfg->is_empty = true;
else

14
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
View File

@@ -2557,6 +2557,9 @@ static const struct rk_gmac_ops rv1126_ops = {
#define RV1126B_RK_MACPHY_DISABLE 0
#define RV1126B_RK_MACPHY_ENABLE BIT(31)
#define RV1126B_RK_MACPHY_EXTCLK_SEL_OUTPUT 0
#define RV1126B_RK_MACPHY_EXTCLK_SEL_INPUT BIT(8)
#define RV1126B_RK_MACPHY_CLK_24M 0
#define RV1126B_RK_MACPHY_CLK_50M BIT(11)
@@ -2680,11 +2683,14 @@ static void rv1126b_integrated_phy_power(struct rk_priv_data *priv, bool up)
usleep_range(20, 40);
if (priv->clk_phy_rate == 50000000)
regmap_write(priv->grf, RV1126B_VI_GRF_RK_MACPHY_CON2,
RV1126B_RK_MACPHY_CLK_50M);
value = RV1126B_RK_MACPHY_CLK_50M;
else
regmap_write(priv->grf, RV1126B_VI_GRF_RK_MACPHY_CON2,
RV1126B_RK_MACPHY_CLK_24M);
value = RV1126B_RK_MACPHY_CLK_24M;
value |= priv->clock_input ? RV1126B_RK_MACPHY_EXTCLK_SEL_INPUT :
RV1126B_RK_MACPHY_EXTCLK_SEL_OUTPUT;
regmap_write(priv->grf, RV1126B_VI_GRF_RK_MACPHY_CON2, value);
regmap_write(priv->grf, RV1126B_VI_GRF_RK_MACPHY_CON0,
RV1126B_RK_MACPHY_PHY_ID | RV1126B_RK_MACPHY_PHY_ADDR);

1367
drivers/power/supply/rk817_battery.c
View File

File diff suppressed because it is too large Load Diff

87
drivers/rtc/rtc-rockchip.c
View File

@@ -710,92 +710,6 @@ static int rv1106_rtc_test_start(struct regmap *regmap)
return ret;
}
static int rv1126b_rtc_test_start(struct regmap *regmap)
{
u64 camp, tcamp;
u32 count[4], counts, ref;
int ret, done = 0, trim_dir, c_hour, c_day, c_mon;
ret = rockchip_rtc_write(regmap, RV1126B_RTC_TEST_LEN,
CLK32K_TEST_LEN);
if (ret) {
pr_err("%s:Failed to update RTC CLK32K TEST LEN: %d\n",
__func__, ret);
return ret;
}
ret = rockchip_rtc_update_bits(regmap, RV1126B_RTC_TEST_ST,
RV1126B_CLK32K_TEST_START,
RV1126B_CLK32K_TEST_START);
if (ret) {
pr_err("%s:Failed to update RTC CLK32K TEST STATUS : %d\n",
__func__, ret);
return ret;
}
ret = regmap_read_poll_timeout(regmap, RV1126B_RTC_TEST_ST, done,
(done & RV1126B_CLK32K_TEST_DONE), 20000, RTC_TIMEOUT);
if (ret)
pr_err("%s:timeout waiting for RTC TEST STATUS : %d\n", __func__, ret);
ret = regmap_bulk_read(regmap,
RV1126B_RTC_CNT_0,
count, 4);
if (ret) {
pr_err("Failed to read RTC count REG: %d\n", ret);
return ret;
}
counts = count[0] | (count[1] << 8) |
(count[2] << 16) | (count[3] << 24);
ref = CLK32K_TEST_REF_CLK * (CLK32K_TEST_LEN + 1);
if (counts > ref) {
trim_dir = 0;
camp = (60ULL / (CLK32K_TEST_LEN + 1)) * (32768 * (counts - ref));
do_div(camp, (CLK32K_TEST_REF_CLK / 1000));
} else {
trim_dir = CLK32K_COMP_DIR_ADD;
camp = (60ULL / (CLK32K_TEST_LEN + 1)) * (32768 * (counts - ref));
do_div(camp, (CLK32K_TEST_REF_CLK / 1000));
}
tcamp = camp;
do_div(tcamp, 1000);
c_hour = tcamp & 0xff;
c_day = (tcamp & 0x7f00) >> 8;
if (c_hour > 1)
rockchip_rtc_write(regmap, RTC_COMP_H, bin2bcd(c_hour));
else
rockchip_rtc_write(regmap, RTC_COMP_H, CLK32K_NO_COMP);
if (c_day > 1)
rockchip_rtc_write(regmap, RTC_COMP_D, bin2bcd(c_day) | trim_dir);
else
rockchip_rtc_write(regmap, RTC_COMP_D, CLK32K_NO_COMP | trim_dir);
c_mon = do_div(camp, 1000);
if (c_mon > 0xff)
c_mon = 0xff;
if (c_mon > 1)
rockchip_rtc_write(regmap, RTC_COMP_M, bin2bcd(c_mon));
else
rockchip_rtc_write(regmap, RTC_COMP_M, CLK32K_NO_COMP);
ret = regmap_read(regmap, RTC_CTRL, &done);
if (ret) {
pr_err("Failed to read RTC_CTRL: %d\n", ret);
return ret;
}
ret = rockchip_rtc_update_bits(regmap, RTC_CTRL,
CLK32K_COMP_EN | RV1126B_COMP_MODE,
CLK32K_COMP_EN | RV1126B_COMP_MODE);
if (ret) {
pr_err("%s:Failed to update RTC CTRL : %d\n", __func__, ret);
return ret;
}
return ret;
}
/*
* Due to the analog generator 32k clock affected by
* temperature, voltage, clock precision need test
@@ -925,7 +839,6 @@ static const struct rockchip_rtc_chip rv1103b_rtc_data = {
static const struct rockchip_rtc_chip rv1126b_rtc_data = {
.initialize = rv1103b_rtc_init,
.clamp_en = rv1126b_rtc_clamp,
.test_start = rv1126b_rtc_test_start,
};
static const struct of_device_id rockchip_rtc_of_match[] = {

7
drivers/thermal/rockchip_thermal.c
View File

@@ -347,8 +347,8 @@ struct rockchip_thermal_data {
#define RV1126B_TARGET_WIDTH 24000
#define RV1126B_DEF_BIAS 32
#define RV1126B_BIAS_MASK (0x7f << 16)
#define RV1126B_HW_CTRL BIT(15)
#define RV1126B_HW_CTRL_MASK (BIT(15) << 16)
#define RV1126B_SW_CTRL 0x8028
#define RV1126B_SW_CTRL_MASK (0x8078 << 16)
#define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
#define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
@@ -1705,7 +1705,8 @@ static void rv1126b_tsadc_phy_init(struct device *dev, struct regmap *grf,
phy_cfg->bias | RV1126B_BIAS_MASK);
regmap_write(grf, RV1126B_GRF_TSADC_CON6,
RV1126B_CH_EN | RV1126B_CH_EN_MASK);
regmap_write(grf, RV1126B_GRF_TSADC_CON0, RV1126B_HW_CTRL_MASK);
regmap_write(grf, RV1126B_GRF_TSADC_CON0,
RV1126B_SW_CTRL | RV1126B_SW_CTRL_MASK);
regmap_write(grf, RV1126B_GRF_TSADC_CON1,
RV1126B_UNLOCK_VALUE | RV1126B_UNLOCK_VALUE_MASK);
regmap_write(grf, RV1126B_GRF_TSADC_CON1,

18
include/soc/rockchip/rockchip_rockit.h
View File

@@ -57,6 +57,24 @@ struct ISP_VIDEO_FRAMES {
u64 u64PrivateData;
u32 u32FrameFlag; /* FRAME_FLAG_E, can be OR operation. */
u8 ispEncCnt;
u32 hdr;
u32 rolling_shutter_skew;
/* linear or hdr short frame */
u32 sensor_exposure_time;
u32 sensor_analog_gain;
u32 sensor_digital_gain;
u32 isp_digital_gain;
/* hdr mid-frame */
u32 sensor_exposure_time_m;
u32 sensor_analog_gain_m;
u32 sensor_digital_gain_m;
u32 isp_digital_gain_m;
/* hdr long frame */
u32 sensor_exposure_time_l;
u32 sensor_analog_gain_l;
u32 sensor_digital_gain_l;
u32 isp_digital_gain_l;
};
struct rkisp_dev_cfg {

15
sound/soc/rockchip/rockchip_pdm_v2.c
View File

@@ -136,7 +136,7 @@ static void rockchip_pdm_v2_rxctrl(struct rk_pdm_v2_dev *pdm, int on)
static int rockchip_pdm_v2_set_samplerate(struct rk_pdm_v2_dev *pdm, unsigned int samplerate)
{
unsigned int upsamplerate, mclk, ratio, scale = 0;
int index, ret = 0;
int i, index, ret = 0;
index = get_pdm_v2_clkref(pdm, samplerate);
if (index < 0)
@@ -152,6 +152,17 @@ static int rockchip_pdm_v2_set_samplerate(struct rk_pdm_v2_dev *pdm, unsigned in
if (ret)
return ret;
if (pdm->version == RV1126B_PDM) {
/* calculate the data shift if not set by dts.
* Set default phase offset of 180 degrees.
*/
mclk = clk_get_rate(pdm->clk);
if (pdm->data_shift[0] == 0) {
for (i = 0; i < PDM_V2_CHANNEL_MAX; i++)
pdm->data_shift[i] = (mclk / upsamplerate / 2) + 1;
}
}
ratio = upsamplerate / samplerate / 2;
switch (ratio) {
case 8:
@@ -241,6 +252,7 @@ static int rockchip_pdm_v2_hw_params(struct snd_pcm_substream *substream,
PDM_V2_FILT1_HPF_V2_FREQ_60);
}
rockchip_pdm_v2_set_samplerate(pdm, params_rate(params));
if (pdm->version == RV1126B_PDM) {
/* PDM data shift */
n = params_channels(params);
@@ -266,7 +278,6 @@ static int rockchip_pdm_v2_hw_params(struct snd_pcm_substream *substream,
}
}
rockchip_pdm_v2_set_samplerate(pdm, params_rate(params));
val = 0;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE: