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arm64: dts: rockchip: rk3562-evb1-lp4x-v10: Change clkin div to 5 for aclk vo

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The dclk vop is 132MHz, the aclk vop can be reduced appropriately.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I80d060fd90e013aaa1eea4d94868731e3cf02ffb
This commit is contained in:
Finley Xiao
2023-08-17 09:26:00 +08:00
committed by Tao Huang
parent 26d58236a5
commit 24ea6649ad
1 changed files with 12 additions and 0 deletions
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12
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi
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@@ -179,6 +179,18 @@
};
};
&bus_soc {
rockchip,soc-bus-table = <0 0x00a000a8 0x7001>,
<1 0x00a000a8 0x7c39>,
<2 0x00a000a8 0x7c39>,
<3 0x00a000a8 0x7c39>,
<4 0x00a000a5 0xb007>,
<5 0x00a000a8 0x7034>,
<6 0x00a000a8 0x7034>,
<7 0x00a000a8 0x7034>,
<8 0x00a000a8 0x7001>;
};
&gmac0 {
/* Use rgmii-rxid mode to disable rx delay inside Soc */
phy-mode = "rgmii-rxid";