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Merge commit '89b7bdea30f21459fa9661cd26ac9fd59f9da148'

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* commit '89b7bdea30f21459fa9661cd26ac9fd59f9da148':
  drm/rockchip: vop2: get correct dclk source when fixup dclk rate
  phy: rockchip: inno-usb2: Clear charger state in host mode
  arm64: dts: rockchip: rk3576: Change low temp config for opp table
  arm64: dts: rockchip: init rk806 pwrctrl3 output low for rk3576-eink
  arm64: dts: rockchip: rk3588-rk806: Change cpu init volt to 800mV
  arm64: dts: rockchip: rk3588s: Change low temp to 15000mC
  arm64: dts: rockchip: rk3588s: Change cpu low temp min vlot to 800mV
  media: i2c: ov16885: fix vflip ghost issue
  drm/rockchip: dw-dp: select encoder by the correct crtc

Change-Id: If8eaf73f22d0637b1e90be78a9cbcbe5585255ad
This commit is contained in:
Tao Huang
2024-05-30 20:44:51 +08:00
parent de10b3731d 89b7bdea30
commit 26a451843b
10 changed files with 97 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi
View File

@@ -63,6 +63,9 @@
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
pinctrl-1 = <&rk806_dvs2_pwrdn>;
//for rk3576 have ultra sleep circuit design
pwrctrl3_output = <0>;
/* 2800mv-3500mv */
low_voltage_threshold = <3000>;
/* 2700mv-3400mv */

18
arch/arm64/boot/dts/rockchip/rk3576.dtsi
View File

@@ -427,8 +427,8 @@
rockchip,reboot-freq = <1416000>;
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
rockchip,low-temp-min-volt = <750000>;
rockchip,low-temp = <15000>;
rockchip,low-temp-min-volt = <800000>;
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
@@ -545,8 +545,8 @@
rockchip,reboot-freq = <1608000>;
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
rockchip,low-temp-min-volt = <750000>;
rockchip,low-temp = <15000>;
rockchip,low-temp-min-volt = <800000>;
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
@@ -821,7 +821,7 @@
rockchip,early-min-microvolt = <0 750000>; /* <vdd_ddr vdd_logic> */
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
rockchip,low-temp = <15000>;
rockchip,low-temp-min-volt = <750000>;
rockchip,leakage-voltage-sel = <
@@ -2057,7 +2057,7 @@
<&cru PCLK_NPUTOP_ROOT>;
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
rockchip,low-temp = <15000>;
rockchip,low-temp-min-volt = <750000>;
opp-300000000 {
@@ -2180,7 +2180,7 @@
rockchip,opp-clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>;
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
rockchip,low-temp = <15000>;
rockchip,low-temp-min-volt = <750000>;
opp-300000000 {
@@ -2911,6 +2911,10 @@
rockchip,early-min-microvolt = <750000>; /* vdd_logic */
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <15000>;
rockchip,low-temp-min-volt = <750000>;
rockchip,init-freq = <702000>; /* KHz */
rockchip,leakage-voltage-sel = <

6
arch/arm64/boot/dts/rockchip/rk3588-rk806-dual.dtsi
View File

@@ -532,6 +532,7 @@
vdd_cpu_big1_s0: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <800000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -544,6 +545,7 @@
vdd_cpu_big0_s0: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <800000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -556,6 +558,7 @@
vdd_cpu_lit_s0: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <800000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
@@ -580,6 +583,7 @@
vdd_cpu_big1_mem_s0: DCDC_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <800000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -593,6 +597,7 @@
vdd_cpu_big0_mem_s0: DCDC_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <800000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -617,6 +622,7 @@
vdd_cpu_lit_mem_s0: DCDC_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <800000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;

1
arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi
View File

@@ -165,6 +165,7 @@
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <800000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;

6
arch/arm64/boot/dts/rockchip/rk3588s-rk806-dual.dtsi
View File

@@ -531,6 +531,7 @@
vdd_cpu_big1_s0: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <800000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -543,6 +544,7 @@
vdd_cpu_big0_s0: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <800000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -555,6 +557,7 @@
vdd_cpu_lit_s0: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <800000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
@@ -580,6 +583,7 @@
vdd_cpu_big1_mem_s0: DCDC_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <800000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -593,6 +597,7 @@
vdd_cpu_big0_mem_s0: DCDC_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <800000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -617,6 +622,7 @@
vdd_cpu_lit_mem_s0: DCDC_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <800000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;

18
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@@ -705,8 +705,8 @@
rockchip,reboot-freq = <1416000>; /* KHz */
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
rockchip,low-temp-min-volt = <750000>;
rockchip,low-temp = <15000>;
rockchip,low-temp-min-volt = <800000>;
rockchip,high-temp = <85000>;
rockchip,high-temp-max-freq = <1608000>;
@@ -970,8 +970,8 @@
rockchip,reboot-freq = <1800000>; /* KHz */
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
rockchip,low-temp-min-volt = <750000>;
rockchip,low-temp = <15000>;
rockchip,low-temp-min-volt = <800000>;
rockchip,high-temp = <85000>;
rockchip,high-temp-max-freq = <2208000>;
@@ -1303,8 +1303,8 @@
rockchip,reboot-freq = <1800000>; /* KHz */
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
rockchip,low-temp-min-volt = <750000>;
rockchip,low-temp = <15000>;
rockchip,low-temp-min-volt = <800000>;
rockchip,high-temp = <85000>;
rockchip,high-temp-max-freq = <2208000>;
@@ -1769,7 +1769,7 @@
58 254 3
>;
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
rockchip,low-temp = <15000>;
rockchip,low-temp-min-volt = <750000>;
/* RK3588 dmc OPPs */
@@ -2432,7 +2432,7 @@
intermediate-threshold-freq = <400000>; /* KHz */
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
rockchip,low-temp = <15000>;
rockchip,low-temp-min-volt = <750000>;
rockchip,high-temp = <85000>;
rockchip,high-temp-max-freq = <800000>;
@@ -3525,7 +3525,7 @@
rockchip,init-freq = <1000000>; /* KHz */
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
rockchip,low-temp = <15000>;
rockchip,low-temp-min-volt = <750000>;
rockchip,high-temp = <85000>;
rockchip,high-temp-max-freq = <800000>;

3
drivers/gpu/drm/rockchip/dw-dp.c
View File

@@ -3329,7 +3329,8 @@ static void dw_dp_mst_assigned_encoder(struct dw_dp *dp, struct drm_atomic_state
if (!connector->state->crtc && new_con_state->crtc) {
availble_encoders = encoder_mask ^ connector->possible_encoders;
for (i = 0; i < dp->mst_port_num; i++) {
if (drm_encoder_crtc_ok(&dp->mst_enc[i].encoder, crtc) &&
if (drm_encoder_crtc_ok(&dp->mst_enc[i].encoder,
new_con_state->crtc) &&
(availble_encoders &
drm_encoder_mask(&dp->mst_enc[i].encoder))) {
mst_conn->mst_enc = &dp->mst_enc[i];

6
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -7896,8 +7896,10 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
drm_connector_list_iter_end(&conn_iter);
if (adj_mode->crtc_clock <= VOP2_MAX_DCLK_RATE) {
adj_mode->crtc_clock = rockchip_drm_dclk_round_rate(vop2->version, vp->dclk,
adj_mode->crtc_clock * 1000);
adj_mode->crtc_clock =
rockchip_drm_dclk_round_rate(vop2->version,
vp->dclk_parent ? vp->dclk_parent : vp->dclk,
adj_mode->crtc_clock * 1000);
adj_mode->crtc_clock = DIV_ROUND_UP(adj_mode->crtc_clock, 1000);
}
return true;

57
drivers/media/i2c/ov16885.c
View File

@@ -5,6 +5,9 @@
* Copyright (C) 2023 Rockchip Electronics Co., Ltd.
*
* V0.0X01.0X00 first version.
* V0.0X01.0X01
* 1. fix vflip ghost issue.
* 2. add write/read reg failed log.
*
*/
//#define DEBUG
@@ -27,7 +30,7 @@
#include <media/v4l2-subdev.h>
#include <linux/pinctrl/consumer.h>
#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
#define OV16885_MAJOR_I2C_ADDR 0x36
#define OV16885_MINOR_I2C_ADDR 0x10
@@ -70,6 +73,8 @@
#define OV16885_SOFTWARE_RESET_REG 0x0103
#define OV16885_REG_ISP_X_WIN 0x3810
#define OV16885_REG_ISP_Y_WIN 0x3812
#define OV16885_REG_SYNC_FIF0_CTRL 0x4500
#define OV16885_GROUP_UPDATE_ADDRESS 0x3208
#define OV16885_GROUP_UPDATE_START_DATA 0x00
@@ -958,8 +963,11 @@ static int ov16885_write_reg(struct i2c_client *client, u16 reg,
while (val_i < 4)
buf[buf_i++] = val_p[val_i++];
if (i2c_master_send(client, buf, len + 2) != len + 2)
if (i2c_master_send(client, buf, len + 2) != len + 2) {
dev_err(&client->dev,
"write reg(0x%x val:0x%x)!\n", reg, val);
return -EIO;
}
return 0;
}
@@ -1005,8 +1013,11 @@ static int ov16885_read_reg(struct i2c_client *client, u16 reg,
msgs[1].buf = &data_be_p[4 - len];
ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret != ARRAY_SIZE(msgs))
if (ret != ARRAY_SIZE(msgs)) {
dev_err(&client->dev,
"read reg(0x%x val:0x%x) failed !\n", reg, *val);
return -EIO;
}
*val = be32_to_cpu(data_be);
@@ -1717,7 +1728,7 @@ static int ov16885_set_ctrl(struct v4l2_ctrl *ctrl)
struct i2c_client *client = ov16885->client;
s64 max;
int ret = 0;
u32 val = 0, x_win = 0;
u32 val = 0, x_win = 0, y_win = 0, sync_ctrl = 0;
/* Propagate change of current control to all related controls */
switch (ctrl->id) {
@@ -1801,12 +1812,46 @@ static int ov16885_set_ctrl(struct v4l2_ctrl *ctrl)
OV16885_REG_VALUE_08BIT,
&val);
if (ctrl->val)
val |= FLIP_BIT_MASK;
val |= (FLIP_BIT_MASK | BIT(6));
else
val &= ~FLIP_BIT_MASK;
val &= ~(FLIP_BIT_MASK | BIT(6));
ret |= ov16885_read_reg(ov16885->client, OV16885_REG_ISP_Y_WIN,
OV16885_REG_VALUE_16BIT,
&y_win);
if ((y_win == 0x0008) && (ctrl->val)) {
y_win = 0x0009;
sync_ctrl = 0x80;
} else if ((y_win == 0x0009) && (!(ctrl->val))) {
y_win = 0x0008;
sync_ctrl = 0x00;
}
ret |= ov16885_write_reg(ov16885->client,
OV16885_GROUP_UPDATE_ADDRESS,
OV16885_REG_VALUE_08BIT,
OV16885_GROUP_UPDATE_START_DATA);
ret |= ov16885_write_reg(ov16885->client, OV16885_FLIP_REG,
OV16885_REG_VALUE_08BIT,
val);
ret |= ov16885_write_reg(ov16885->client, OV16885_REG_ISP_Y_WIN,
OV16885_REG_VALUE_16BIT,
y_win);
ret |= ov16885_write_reg(ov16885->client, OV16885_REG_SYNC_FIF0_CTRL,
OV16885_REG_VALUE_08BIT,
sync_ctrl);
ret |= ov16885_write_reg(ov16885->client,
OV16885_GROUP_UPDATE_ADDRESS,
OV16885_REG_VALUE_08BIT,
OV16885_GROUP_UPDATE_END_DATA);
ret |= ov16885_write_reg(ov16885->client,
OV16885_GROUP_UPDATE_ADDRESS,
OV16885_REG_VALUE_08BIT,
OV16885_GROUP_UPDATE_LAUNCH);
break;
default:
dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",

4
drivers/phy/rockchip/phy-rockchip-inno-usb2.c
View File

@@ -1253,6 +1253,10 @@ static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
mutex_unlock(&rport->mutex);
rockchip_usb2phy_power_on(rport->phy);
if (extcon_get_state(rphy->edev, cable)) {
extcon_set_state_sync(rphy->edev, cable, false);
cable = EXTCON_NONE;
}
return;
} else if (rport->vbus_attached) {
dev_dbg(&rport->phy->dev, "vbus_attach\n");