shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 19:30:30 +09:00
Code Issues Packages Projects Releases Wiki Activity

ARM: dts: rockchip: rk312x: modify dsi node description

Browse Source 
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I849b799c4346c1ab039d4650b0e7c0fd27d6cf58
This commit is contained in:
Guochun Huang
2022-10-19 05:56:47 +00:00
committed by Tao Huang
parent ddaecd89d2
commit 2aaca40d95
1 changed files with 7 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
arch/arm/boot/dts/rk312x.dtsi
View File

@@ -670,12 +670,12 @@
compatible = "rockchip,rk3128-mipi-dsi";
reg = <0x10110000 0x4000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>, <&video_phy>;
clock-names = "pclk", "h2p", "hs_clk";
clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>;
clock-names = "pclk", "hclk";
resets = <&cru SRST_VIO_MIPI_DSI>;
reset-names = "apb";
phys = <&video_phy>;
phy-names = "mipi_dphy";
phy-names = "dphy";
power-domains = <&power RK3128_PD_VIO>;
rockchip,grf = <&grf>;
#address-cells = <1>;
@@ -996,14 +996,15 @@
};
video_phy: video-phy@20038000 {
compatible = "rockchip,rk3128-video-phy";
compatible = "rockchip,rk3128-dsi-dphy", "rockchip,rk3128-video-phy";
reg = <0x20038000 0x4000>, <0x10110000 0x4000>;
reg-names = "phy", "host";
clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>,
<&cru PCLK_MIPI>;
clock-names = "ref", "pclk_phy", "pclk_host";
clock-names = "ref", "pclk", "pclk_host";
#clock-cells = <0>;
resets = <&cru SRST_MIPIPHY_P>;
reset-names = "rst";
reset-names = "apb";
power-domains = <&power RK3128_PD_VIO>;
#phy-cells = <0>;
status = "disabled";