clk/rockchip/regmap: pll: limit postdiv2 max value

Change-Id: I0dcb5001960cf0dcaa82f992b7d428f6d08678ff Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2026-06-07 19:30:30 +09:00 · 2020-10-12 11:33:51 +08:00
parent 0d3f9ae026
commit 459a08874a
1 changed files with 3 additions and 0 deletions
--- a/drivers/clk/rockchip/regmap/clk-regmap-pll.c
+++ b/drivers/clk/rockchip/regmap/clk-regmap-pll.c
@@ -152,6 +152,9 @@ static long clk_pll_round_rate(unsigned long fin, unsigned long fout,
 				break;
 		}

+		if (_postdiv2 > 7)
+			return -EINVAL;
+
 		fout *= _postdiv1 * _postdiv2;
 	} else {
 		_postdiv1 = 1;