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Merge commit 'e15707617c807e82a706dfdd2240c83d62f2634e'

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* commit 'e15707617c807e82a706dfdd2240c83d62f2634e':
  PCI: rockchip: dw: remove wakeup if attached device is down
  PCI: rockchip: dw: Add runtime pm support
  drm/rockchip: dw-dp: Include linux/random.h
  arm64: dts: rockchip: rk3576-eink: adjust dmc freq threshold
  arm64: dts: rockchip: rk3562j: add opp-table for overdrive mode
  arm64: dts: rockchip: rk3562j: remove duplicate can node

Change-Id: I4ad50344c4f921a11602e98960a8ac5d79377f0c
This commit is contained in:
Tao Huang
2024-10-21 19:43:40 +08:00
parent 379d988cd4 e15707617c
commit 793250939e
5 changed files with 129 additions and 27 deletions
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114
arch/arm64/boot/dts/rockchip/rk3562.dtsi
View File

@@ -396,6 +396,50 @@
opp-microvolt-L0 = <925000 925000 1150000>;
clock-latency-ns = <40000>;
};
/*
* The Max frequency is 1200MHz in default normal mode.
* The Max frequency is 1800MHz in overdrive mode,
* but under the overdrive mode for a long time,
* the chipset may shorten the lifetime, especially in high
* temperature condition. Disable overdrive opps by default
* and you can enable them in dts file.
*/
cpu_opp_j_od_1416000000: opp-j-od-1416000000 {
opp-supported-hw = <0x04 0xffff>;
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1000000 1000000 1150000>;
opp-microvolt-L0 = <1000000 1000000 1150000>;
opp-microvolt-L1 = <975000 975000 1150000>;
opp-microvolt-L2 = <950000 950000 1150000>;
opp-microvolt-L3 = <925000 925000 1150000>;
opp-microvolt-L4 = <900000 900000 1150000>;
clock-latency-ns = <40000>;
status = "disabled";
};
cpu_opp_j_od_1608000000: opp-j-od-1608000000 {
opp-supported-hw = <0x04 0xffff>;
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <1037500 1037500 1150000>;
opp-microvolt-L0 = <1037500 1037500 1150000>;
opp-microvolt-L1 = <1012500 1012500 1150000>;
opp-microvolt-L2 = <987500 987500 1150000>;
opp-microvolt-L3 = <962500 962500 1150000>;
opp-microvolt-L4 = <937500 937500 1150000>;
clock-latency-ns = <40000>;
status = "disabled";
};
cpu_opp_j_od_1800000000: opp-j-od-1800000000 {
opp-supported-hw = <0x04 0xffff>;
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1125000 1125000 1150000>;
opp-microvolt-L0 = <1125000 1125000 1150000>;
opp-microvolt-L1 = <1100000 1100000 1150000>;
opp-microvolt-L2 = <1075000 1075000 1150000>;
opp-microvolt-L3 = <1050000 1050000 1150000>;
opp-microvolt-L4 = <1025000 1025000 1150000>;
clock-latency-ns = <40000>;
status = "disabled";
};
};
arm_pmu: arm-pmu {
@@ -1654,8 +1698,47 @@
opp-j-700000000 {
opp-supported-hw = <0x04 0xffff>;
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <925000 925000 1000000>;
opp-microvolt = <900000 900000 1000000>;
opp-microvolt-L0 = <925000 925000 1000000>;
};
/* The Max frequency is 700MHz in default normal mode.
* The Max frequency is 1000MHz in overdrive mode,
* but under the overdrive mode for a long time,
* the chipset may shorten the lifetime, especially in high
* temperature condition. Disable overdrive opps by default
* and you can enable them in dts file.
*/
npu_opp_j_od_800000000: opp-j-od-800000000 {
opp-supported-hw = <0x04 0xffff>;
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <975000 975000 1000000>;
opp-microvolt-L0 = <975000 975000 1000000>;
opp-microvolt-L1 = <950000 950000 1000000>;
opp-microvolt-L2 = <925000 925000 1000000>;
opp-microvolt-L3 = <900000 900000 1000000>;
opp-microvolt-L4 = <900000 900000 1000000>;
status = "disabled";
};
npu_opp_j_od_900000000: opp-j-od-900000000 {
opp-supported-hw = <0x04 0xffff>;
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <1000000 1000000 1000000>;
opp-microvolt-L0 = <1000000 1000000 1000000>;
opp-microvolt-L1 = <1000000 1000000 1000000>;
opp-microvolt-L2 = <975000 975000 1000000>;
opp-microvolt-L3 = <950000 950000 1000000>;
opp-microvolt-L4 = <925000 925000 1000000>;
status = "disabled";
};
npu_opp_j_od_1000000000: opp-j-od-1000000000 {
opp-supported-hw = <0x04 0xffff>;
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1000000 1000000 1000000>;
opp-microvolt-L0 = <1000000 1000000 1000000>;
opp-microvolt-L1 = <1000000 1000000 1000000>;
opp-microvolt-L2 = <1000000 1000000 1000000>;
opp-microvolt-L3 = <975000 975000 1000000>;
opp-microvolt-L4 = <950000 950000 1000000>;
status = "disabled";
};
};
@@ -1802,6 +1885,35 @@
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <900000 900000 1000000>;
};
/* The Max frequency is 700MHz in default normal mode.
* The Max frequency is 900MHz in overdrive mode,
* but under the overdrive mode for a long time,
* the chipset may shorten the lifetime, especially in high
* temperature condition. Disable overdrive opps by default
* and you can enable them in dts file.
*/
gpu_opp_j_od_800000000: opp-j-od-800000000 {
opp-supported-hw = <0x04 0xffff>;
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <950000 950000 1000000>;
opp-microvolt-L0 = <950000 950000 1000000>;
opp-microvolt-L1 = <925000 925000 1000000>;
opp-microvolt-L2 = <900000 900000 1000000>;
opp-microvolt-L3 = <875000 875000 1000000>;
opp-microvolt-L4 = <850000 850000 1000000>;
status = "disabled";
};
gpu_opp_j_od_900000000: opp-j-od-900000000 {
opp-supported-hw = <0x04 0xffff>;
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <1000000 1000000 1000000>;
opp-microvolt-L0 = <1000000 1000000 1000000>;
opp-microvolt-L1 = <975000 975000 1000000>;
opp-microvolt-L2 = <950000 950000 1000000>;
opp-microvolt-L3 = <925000 925000 1000000>;
opp-microvolt-L4 = <900000 900000 1000000>;
status = "disabled";
};
};
rkvdec: rkvdec@ff340100 {

24
arch/arm64/boot/dts/rockchip/rk3562j.dtsi
View File

@@ -4,27 +4,3 @@
*/
#include "rk3562.dtsi"
/ {
can0: can@ff600000 {
compatible = "rockchip,rk3562-can";
reg = <0x0 0xff600000 0x0 0x1000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
clock-names = "baudclk", "apb_pclk";
resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
reset-names = "can", "can-apb";
status = "disabled";
};
can1: can@ff610000 {
compatible = "rockchip,rk3562-can";
reg = <0x0 0xff610000 0x0 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
clock-names = "baudclk", "apb_pclk";
resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
reset-names = "can", "can-apb";
status = "disabled";
};
};

2
arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi
View File

@@ -43,6 +43,8 @@
&dmc {
wait-mode = <DMC_WAIT_MODE_EBC_VBANK>;
upthreshold = <50>;
downdifferential = <25>;
};
&ebc {

1
drivers/gpu/drm/rockchip/dw-dp.c
View File

@@ -32,6 +32,7 @@
#include <linux/irq.h>
#include <linux/of_device.h>
#include <linux/of_graph.h>
#include <linux/random.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/gpio/consumer.h>

15
drivers/pci/controller/dwc/pcie-dw-rockchip.c
View File

@@ -18,6 +18,7 @@
#include <linux/of_pci.h>
#include <linux/phy/phy.h>
#include <linux/phy/pcie.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/rfkill-wlan.h>
@@ -1506,6 +1507,9 @@ static int rk_pcie_really_probe(void *p)
if (ret)
goto release_driver;
pm_runtime_enable(dev);
pm_runtime_get_sync(pci->dev);
reset_control_assert(rk_pcie->rsts);
udelay(10);
@@ -1576,7 +1580,8 @@ static int rk_pcie_really_probe(void *p)
dw_pcie_dbi_ro_wr_dis(pci);
/* 7. framework misc settings */
device_init_wakeup(dev, true);
if (rk_pcie->skip_scan_in_resume)
device_init_wakeup(dev, true);
device_enable_async_suspend(dev); /* Enable async system PM for multiports SoC */
return 0;
@@ -1591,6 +1596,8 @@ disable_phy:
disable_clk:
clk_bulk_disable_unprepare(rk_pcie->clk_cnt, rk_pcie->clks);
disable_vpcie3v3:
pm_runtime_put(dev);
pm_runtime_disable(dev);
rk_pcie_disable_power(rk_pcie);
release_driver:
if (IS_ENABLED(CONFIG_PCIE_RK_THREADED_INIT))
@@ -1741,8 +1748,10 @@ static int __maybe_unused rockchip_dw_pcie_suspend(struct device *dev)
*/
if (rk_pcie->skip_scan_in_resume) {
rfkill_get_wifi_power_state(&power);
if (!power)
if (!power) {
device_init_wakeup(dev, false);
goto no_l2;
}
}
/* 2. Broadcast PME_Turn_Off Message */
@@ -1856,6 +1865,8 @@ static int __maybe_unused rockchip_dw_pcie_resume(struct device *dev)
dw_pcie_dbi_ro_wr_dis(rk_pcie->pci);
rk_pcie->in_suspend = false;
if (rk_pcie->skip_scan_in_resume)
device_init_wakeup(dev, true);
return 0;
err: