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clk: rockchip: fix up the frac clk get rate error

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support fractional divider with only one level parent clock

Change-Id: I6593f908edf4454ef03255080bf9ac1d72c6f64e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2018-05-28 16:56:50 +08:00
committed by Tao Huang
parent c64eb759a8
commit 88ec34820f
1 changed files with 10 additions and 5 deletions
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15
drivers/clk/rockchip/clk.c
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@@ -166,11 +166,16 @@ static void rockchip_fractional_approximation(struct clk_hw *hw,
if (((rate * 20 > p_rate) && (p_rate % rate != 0)) ||
(fd->max_prate && fd->max_prate < p_rate)) {
p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
p_parent_rate = clk_hw_get_rate(p_parent);
*parent_rate = p_parent_rate;
if (fd->max_prate && p_parent_rate > fd->max_prate) {
div = DIV_ROUND_UP(p_parent_rate, fd->max_prate);
*parent_rate = p_parent_rate / div;
if (!p_parent) {
*parent_rate = p_rate;
} else {
p_parent_rate = clk_hw_get_rate(p_parent);
*parent_rate = p_parent_rate;
if (fd->max_prate && p_parent_rate > fd->max_prate) {
div = DIV_ROUND_UP(p_parent_rate,
fd->max_prate);
*parent_rate = p_parent_rate / div;
}
}
if (*parent_rate < rate * 20) {