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clk: rockchip: pll: Add ROCKCHIP_PLL_FIXED_MODE for pll_rk3036/rk3328 type

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PLL can be normal mode only.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I331e107b561047aa6b46a6c2f7df539a77a6da2d
This commit is contained in:
Joseph Chen
2022-11-04 01:32:39 +00:00
committed by Tao Huang
parent ee5af82a6f
commit a1a02755f2
2 changed files with 11 additions and 4 deletions
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10
drivers/clk/rockchip/clk-pll.c
View File

@@ -578,10 +578,12 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
rockchip_rk3036_pll_get_params(pll, &cur);
cur.rate = 0;
cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
if (cur_parent == PLL_MODE_NORM) {
pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
rate_change_remuxed = 1;
if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) {
cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
if (cur_parent == PLL_MODE_NORM) {
pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
rate_change_remuxed = 1;
}
}
/* update pll values */

5
drivers/clk/rockchip/clk.h
View File

@@ -505,7 +505,12 @@ struct rockchip_pll_clock {
struct rockchip_pll_rate_table *rate_table;
};
/*
* PLL flags
*/
#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
/* normal mode only. now only for pll_rk3036, pll_rk3328 type */
#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
_lshift, _pflags, _rtable) \