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* commit 'a30a6043181668fa1856337dd99258e88972e649': (56 commits)
  iio: adc: gpio_muxadc: Fix typo in Rockchip copyright notice
  mtd: rknand: Fix typo in Rockchip copyright notice
  net: ethernet: stmmac: Fix typo in Rockchip copyright notice
  net: phy: rk630: Fix typo in Rockchip copyright notice
  pinctrl: max96745: Fix typo in Rockchip copyright notice
  pinctrl: max96755f: Fix typo in Rockchip copyright notice
  power: ec_battery: Fix typo in Rockchip copyright notice
  pwm: rockchip-i2s: Fix typo in Rockchip copyright notice
  spi: rockchip-slave: Fix typo in Rockchip copyright notice
  thermal: rk_virtual_thermal: Fix typo in Rockchip copyright notice
  usb: typec: tcpci_et7303: Fix typo in Rockchip copyright notice
  usb: typec: tcpci_husb311: Fix typo in Rockchip copyright notice
  video: rockchip: rga: Fix typo in Rockchip copyright notice
  video: rockchip: rga2: Fix typo in Rockchip copyright notice
  video: rockchip: vtunnel: Fix typo in Rockchip copyright notice
  dt-bindings: rockchip: Fix typos in Rockchip copyright notice
  clk: rockchip: Fix typo in Rockchip copyright notice
  dma-buf-cache: Fix typo in Rockchip copyright notice
  mfd: max96745: Fix typo in Rockchip copyright notice
  mfd: max96755f: Fix typo in Rockchip copyright notice
  ...

Change-Id: Iaabf0572112bf160811737fdcc804327ca44eb65
This commit is contained in:
Tao Huang
2025-01-22 19:48:18 +08:00
parent 6b33334fb6 a30a604318
commit aa647f5d3b
69 changed files with 280 additions and 492 deletions
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50
Documentation/devicetree/bindings/video/rockchip_dp.txt
View File

@@ -1,50 +0,0 @@
Rockchip RK3399 specific extensions to the cdn Display Port with rkfb
================================
Required properties:
- compatible: must be "rockchip,rk3399-cdn-dp-fb"
- reg: physical base address of the controller and length
- clocks: from common clock binding: handle to dp clock.
- clock-names: from common clock binding:
Required elements: "core-clk" "pclk" "spdif"
- resets : a list of phandle + reset specifier pairs
- reset-names : string reset name, must be:
"spdif"
- power-domains : power-domain property defined with a phandle
to respective power domain.
- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
- assigned-clock-rates : the DP core clk frequency, shall be: 100000000
- rockchip,grf: this soc should set GRF regs, so need get grf here.
- phys: from general PHY binding: the phandle for the PHY device.
- extcon: extcon specifier for the Power Delivery
- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF
-------------------------------------------------------------------------------
Example:
cdn_dp_fb: dp-fb@fec00000 {
compatible = "rockchip,rk3399-cdn-dp-fb";
reg = <0x0 0xfec00000 0x0 0x100000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
<&cru SCLK_SPDIF_REC_DPTX>;
clock-names = "core-clk", "pclk", "spdif";
assigned-clocks = <&cru SCLK_DP_CORE>;
assigned-clock-rates = <100000000>;
power-domains = <&power RK3399_PD_HDCP>;
phys = <&tcphy0 0>, <&tcphy1 0>;
resets = <&cru SRST_DPTX_SPDIF_REC>;
reset-names = "spdif";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
};

65
Documentation/devicetree/bindings/video/rockchip_fb.txt
View File

@@ -1,65 +0,0 @@
Device-Tree bindings for Rockchip framebuffer.
Required properties:
- compatible: value should be "rockchip,rk-fb".
- rockchip,disp-mode: DUAL :for dual lcdc and dual display;
ONE_DUAL : for one lcdc and dual display.
Example:
DT entry:
fb: fb{
compatible = "rockchip,rk-fb";
rockchip,disp-mode = <DUAL>;
};
Device-Tree bindings for RockChip screen driver
Required properties:
- compatible: value should be "rockchip,screen"
- display-timings: value should be disp_timings, which defined in
lcd-xxx.dtsi file,the file should include by your board dts
Example:
creen: rk_screen{
compatible = "rockchip,screen";
display-timings = <&disp_timings>;
};
/*
* RockChip. LCD_B101ew05 lcd-b101ew05.dtsi
*
*/
/ {
disp_timings: display-timings {
native-mode = <&timing0>;
timing0: timing0 {
screen-type = <SCREEN_LVDS>;
lvds-format = <LVDS_8BIT_2>;
out-face = <OUT_D888_P666>;
clock-frequency = <71000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <100>;
hfront-porch = <18>;
vback-porch = <8>;
vfront-porch = <6>;
hsync-len = <10>;
vsync-len = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};
};
note: reference for display-timing.txt for display-timing bindings

69
Documentation/devicetree/bindings/video/rockchip_lcdc.txt
View File

@@ -1,69 +0,0 @@
Device-Tree bindings for Rockchip SoC display controller (VOP / LCDC)
VOP (Video Output Process) / LCDC is the Display Controller for the
ROCKCHIP series of SoCs which transfers the image data from a video memory
buffer to an external LCD interface.
Required properties:
- compatible: value should be one of the following
"rockchip,rk3288-lcdc"; /* for RK3288 SoCs */
"rockchip,rk3368-lcdc"; /* for RK3368 SoCs */
"rockchip,rk322x-lcdc"; /* for RK322X SoCs */
"rockchip,rk3399-lcdc"; /* for RK3399 SoCs */
- rockchip,prop: set the lcdc as primary or extend display.
- rochchip,pwr18: set the controller IO voltage,0 is 3.3v,1 is 1.8v.
- reg: physical base address and length of the LCDC registers set.
- interrupts: interrupt number to the cpu and interrupt proterties.
- pinctrl-names: must contain a "default" entry.
- pinctrl-0: pin control group to be used for this controller.
- pinctrl-1: pin control group to be used for gpio.
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
- clock-names: list of clock names sorted in the same order as the clocks
property..
Optional Properties:
- rockchip,debug: printk debug message.
- rockchip,mirror: the lcdc mirror function.
- lcd_en:lcd_en: contain power control for lcd.
- rockchip,power_type: power type,GPIO or REGULATOR.
- gpios: pin number for gpio.
- rockchip,delay: delay time after set power.
Example:
SoC specific DT entry:
lcdc1: lcdc@ff940000 {
compatible = "rockchip,rk3288-lcdc";
rockchip,prop = <PRMRY>;
rochchip,pwr18 = <0>;
reg = <0xff940000 0x10000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&lcdc0_lcdc>;
pinctrl-1 = <&lcdc0_gpio>;
status = "disabled";
clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
};
Board specific DT entry:
&lcdc1 {
status = "okay";
power_ctr: power_ctr {
rockchip,debug = <0>;
rockchip,mirror = <NO_MIRROR>;
lcd_en:lcd_en {
rockchip,power_type = <GPIO>;
gpios = <&gpio7 GPIO_A3 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
lcd_cs:lcd_cs {
rockchip,power_type = <GPIO>;
gpios = <&gpio7 GPIO_A4 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
};
};

22
Documentation/devicetree/bindings/video/rockchip_lvds.txt
View File

@@ -1,22 +0,0 @@
The Rockchip display port interface should be configured based on
the type of panel connected to it.
Required properties:
- compatible: value should be "rockchip,rk32-lvds".
- reg: physical base address and length of the LVDS registers set.
- interrupts: interrupt number to the cpu and interrupt proterties.
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
- clock-names: list of clock names sorted in the same order as the clocks
property..
Example:
SoC specific DT entry:
lvds: lvds@ff96c000 {
compatible = "rockchip,rk32-lvds";
reg = <0xff96c000 0x4000>;
clocks = <&clk_gates16 7>;
clock-names = "pclk_lvds";
};

39
Documentation/devicetree/bindings/video/rockchip_mipidsi.txt
View File

@@ -1,39 +0,0 @@
Device-Tree bindings for rockchip mipi dsi driver
Required properties:
- compatible: value should be "rockchip,rk32-dsi".
- rockchip,prop: dsi number.
- reg: physical base address of the hdmi and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
- clocks-names: list of clock names sorted in the same order as the clocks
property. Must contain "pclk_hdmi" and "hdcp_clk_hdmi".
- status: the dsi host status;
<disabled>: open the dsi host;
<okay>:close the dsi host;
Example:
dsihost0: mipi@ff960000{
compatible = "rockchip,rk32-dsi";
rockchip,prop = <0>;
reg = <0xff960000 0x4000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>;
clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
status = "okay";
};
dsihost1: mipi@ff964000{
compatible = "rockchip,rk32-dsi";
rockchip,prop = <1>;
reg = <0xff964000 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>;
clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
status = "okay";
};

173
Documentation/devicetree/bindings/video/rockchip_mipidsi_lcd.txt
View File

@@ -1,173 +0,0 @@
Device-Tree bindings for rockchip mipi dsi lcd driver
Required properties:
- rockchip,screen_init: Whether you need this screen initialization.
<0>: Don't need to be initialized.
<1>: Do need to be initialized.
- rockchip,dsi_lane: mipi lcd data lane number.
- rockchip,dsi_hs_clk: mipi lcd high speed clock.
- rockchip,mipi_dsi_num: mipi lcd dsi number.
- mipi_lcd_rst:mipi_lcd_rst: Should specify pin control groups used for reset this lcd.
- mipi_lcd_en:mipi_lcd_en: Should specify pin control groups used for enable this lcd.
- rockchip,gpios: gpio pin
- rockchip,delay: delay the millisecond.
- rockchip,cmd_debug : debug the cammands.
<0>: close the debug;
<1>: open the debug;
- rockchip,on-cmds1: write cammand to mipi lcd.
- rockchip,cmd_type:
<LPDT>: close the debug;
<HSDT>: open the debug;
- rockchip,dsi_id: write cammand to mipi lcd(left and right).
<0>: left dsi;
<1>: right dsi;
<2>: left and right dsis;
- rockchip,cmd: cammand context.
The first parameter was data type;
The second parameter was index(register);
The third and ... parameter are cammand context;
- rockchip,cmd_delay: delay the millisecond.
- screen-type: mipi lcd type.
<SCREEN_DUAL_MIPI>: Dual channel mipi lcd.
<SCREEN_MIPI>: single channel mipi lcd.
- lvds-format:No relationship.
- out-face: DPI color coding as follows:
<OUT_P888>:24bit
<OUT_P666>:18bit
<OUT_P565>:16bit
- hactive, vactive: display resolution
- hfront-porch, hback-porch, hsync-len: horizontal display timing parameters
in pixels
vfront-porch, vback-porch, vsync-len: vertical display timing parameters in
lines
- clock-frequency: display clock in Hz
- swap-rb :exchange of red and blue.
- swap-rg :exchange of red and green.
- swap-gb :exchange of green and blue.
- hsync-active: hsync pulse is active low/high/ignored
- vsync-active: vsync pulse is active low/high/ignored
- de-active: data-enable pulse is active low/high/ignored
- pixelclk-active: with
- active high = drive pixel data on rising edge/
sample data on falling edge
- active low = drive pixel data on falling edge/
sample data on rising edge
- ignored = ignored
- interlaced (bool): boolean to enable interlaced mode
- doublescan (bool): boolean to enable doublescan mode
All the optional properties that are not bool follow the following logic:
<1>: high active
<0>: low active
omitted: not used on hardware
There are different ways of describing the capabilities of a display. The
devicetree representation corresponds to the one commonly found in datasheets
for displays. If a display supports multiple signal timings, the native-mode
can be specified.
The parameters are defined as:
+----------+-------------------------------------+----------+-------+
| | <20><> | | |
| | |vback_porch | | |
| | <20><> | | |
+----------#######################################----------+-------+
| # <20><> # | |
| # | # | |
| hback # | # hfront | hsync |
| porch # | hactive # porch | len |
|<-------->#<-------+--------------------------->#<-------->|<----->|
| # | # | |
| # |vactive # | |
| # | # | |
| # <20><> # | |
+----------#######################################----------+-------+
| | <20><> | | |
| | |vfront_porch | | |
| | <20><> | | |
+----------+-------------------------------------+----------+-------+
| | <20><> | | |
| | |vsync_len | | |
| | <20><> | | |
+----------+-------------------------------------+----------+-------+
Example:
{
/* about mipi */
disp_mipi_init: mipi_dsi_init{
rockchip,screen_init = <1>;
rockchip,dsi_lane = <4>;
rockchip,dsi_hs_clk = <1020>;
rockchip,mipi_dsi_num = <2>;
};
disp_mipi_power_ctr: mipi_power_ctr {
mipi_lcd_rst:mipi_lcd_rst{
rockchip,gpios = <&gpio7 GPIO_B2 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
/*mipi_lcd_en:mipi_lcd_en {
rockchip,gpios = <&gpio6 GPIO_A7 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};*/
};
disp_mipi_init_cmds: screen-on-cmds {
rockchip,cmd_debug = <0>;
rockchip,on-cmds1 {
rockchip,cmd_type = <LPDT>;
rockchip,dsi_id = <2>;
rockchip,cmd = <0x05 0x01>; //set soft reset
rockchip,cmd_delay = <10>;
};
};
disp_timings: display-timings {
native-mode = <&timing0>;
timing0: timing0 {
screen-type = <SCREEN_DUAL_MIPI>;
lvds-format = <LVDS_8BIT_2>;
out-face = <OUT_P888>;
clock-frequency = <285000000>;
hactive = <2560>;
vactive = <1600>;
hsync-len = <38>;//19
hback-porch = <80>;//40
hfront-porch = <246>;//123
vsync-len = <4>;
vback-porch = <4>;
vfront-porch = <12>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};
};

6
arch/arm/boot/dts/rk3502.dtsi
View File

@@ -1452,9 +1452,15 @@
#reset-cells = <1>;
assigned-clocks =
<&cru CLK_32K_FRAC_MUX>,
<&cru CLK_32K_FRAC>,
<&cru CLK_FRAC_UART_MATRIX0>,
<&cru CLK_FRAC_UART_MATRIX1>;
assigned-clock-parents =
<&cru PLL_V0PLL>;
assigned-clock-rates =
<0>,
<32768>,
<96000000>,
<128000000>;
};

4
arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts
View File

@@ -542,8 +542,8 @@
vccio_acodec: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vccio_acodec";
regulator-state-mem {
regulator-off-in-suspend;

4
arch/arm64/boot/dts/rockchip/rk3566-rk817-eink.dts
View File

@@ -396,8 +396,8 @@
vccio_acodec: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vccio_acodec";
regulator-state-mem {
regulator-off-in-suspend;

4
arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dts
View File

@@ -724,8 +724,8 @@
vccio_acodec: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vccio_acodec";
regulator-state-mem {
regulator-off-in-suspend;

4
arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dts
View File

@@ -542,8 +542,8 @@
vccio_acodec: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vccio_acodec";
regulator-state-mem {
regulator-off-in-suspend;

4
arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dts
View File

@@ -656,8 +656,8 @@
vccio_acodec: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vccio_acodec";
regulator-state-mem {
regulator-off-in-suspend;

7
drivers/clk/rockchip/clk-rk3506.c
View File

@@ -742,9 +742,10 @@ static struct rockchip_clk_branch rk3506_clk_branches[] __initdata = {
COMPOSITE(CLK_REF_OUT1, "clk_ref_out1", clk_ref_out_parents_p, 0,
RK3506_PMU_CLKSEL_CON(1), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK3506_PMU_CLKGATE_CON(1), 5, GFLAGS),
COMPOSITE_DIV_OFFSET(CLK_32K_FRAC, "clk_32k_frac", clk_32k_frac_parents_p, CLK_IGNORE_UNUSED,
RK3506_PMU_CLKSEL_CON(3), 0, 2, MFLAGS,
RK3506_PMU_CLKSEL_CON(2), 0, 32, DFLAGS,
MUX(CLK_32K_FRAC_MUX, "clk_32k_frac_mux", clk_32k_frac_parents_p, 0,
RK3506_PMU_CLKSEL_CON(3), 0, 2, MFLAGS),
COMPOSITE_FRAC(CLK_32K_FRAC, "clk_32k_frac", "clk_32k_frac_mux", 0,
RK3506_PMU_CLKSEL_CON(2), 0,
RK3506_PMU_CLKGATE_CON(1), 6, GFLAGS),
COMPOSITE_NOMUX(CLK_32K_RC, "clk_32k_rc", "clk_rc", CLK_IS_CRITICAL,
RK3506_PMU_CLKSEL_CON(3), 2, 5, DFLAGS,

7
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
View File

@@ -197,6 +197,7 @@
#define HDMI_EARC_MODE BIT(29)
#define DATA_RATE_MASK 0xFFFFFFF
#define HDMI14_MAX_RATE 340000
#define HDMI20_MAX_RATE 600000
#define HDMI_8K60_RATE 2376000
@@ -2382,12 +2383,12 @@ dw_hdmi_rockchip_select_output(struct drm_connector_state *conn_state,
*color_format = RK_IF_FORMAT_YCBCR422;
else if (conn_state->connector->ycbcr_420_allowed &&
drm_mode_is_420(info, &mode) &&
(pixclock >= 594000 && !hdmi->is_hdmi_qp))
(pixclock > HDMI14_MAX_RATE && !hdmi->is_hdmi_qp))
*color_format = RK_IF_FORMAT_YCBCR420;
break;
case RK_IF_FORMAT_YCBCR_LQ:
if (conn_state->connector->ycbcr_420_allowed &&
drm_mode_is_420(info, &mode) && pixclock >= 594000)
drm_mode_is_420(info, &mode) && pixclock > HDMI14_MAX_RATE)
*color_format = RK_IF_FORMAT_YCBCR420;
else if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
*color_format = RK_IF_FORMAT_YCBCR422;
@@ -2396,7 +2397,7 @@ dw_hdmi_rockchip_select_output(struct drm_connector_state *conn_state,
break;
case RK_IF_FORMAT_YCBCR420:
if (conn_state->connector->ycbcr_420_allowed &&
drm_mode_is_420(info, &mode) && pixclock >= 594000)
drm_mode_is_420(info, &mode) && pixclock > HDMI14_MAX_RATE)
*color_format = RK_IF_FORMAT_YCBCR420;
break;
case RK_IF_FORMAT_YCBCR422:

46
drivers/gpu/drm/rockchip/rockchip_drm_debugfs.c
View File

@@ -351,3 +351,49 @@ int rockchip_drm_debugfs_add_regs_write(struct drm_crtc *crtc, struct dentry *ro
return 0;
}
static int rockchip_drm_debugfs_dclk_rate_show(struct seq_file *s, void *data)
{
struct drm_crtc *crtc = s->private;
struct rockchip_drm_private *priv = crtc->dev->dev_private;
int pipe = drm_crtc_index(crtc);
unsigned long rate;
if (!priv->crtc_funcs[pipe]->crtc_get_dclk_rate) {
seq_puts(s, "Not support get rate\n");
return 0;
}
rate = priv->crtc_funcs[pipe]->crtc_get_dclk_rate(crtc);
seq_printf(s, "%lu\n", rate);
return 0;
}
static int rockchip_drm_debugfs_dclk_rate_open(struct inode *inode, struct file *file)
{
struct drm_crtc *crtc = inode->i_private;
return single_open(file, rockchip_drm_debugfs_dclk_rate_show, crtc);
}
static const struct file_operations rockchip_drm_debugfs_dclk_rate_ops = {
.owner = THIS_MODULE,
.open = rockchip_drm_debugfs_dclk_rate_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
int rockchip_drm_debugfs_add_dclk_rate(struct drm_crtc *crtc, struct dentry *root)
{
struct dentry *ent;
ent = debugfs_create_file("calculated_dclk_rate", 0644, root, crtc,
&rockchip_drm_debugfs_dclk_rate_ops);
if (!ent)
DRM_ERROR("Failed to add dclk_rate for debugfs\n");
return 0;
}

7
drivers/gpu/drm/rockchip/rockchip_drm_debugfs.h
View File

@@ -37,6 +37,7 @@ rockchip_drm_crtc_dump_plane_buffer(struct drm_crtc *crtc)
#endif
int rockchip_drm_debugfs_add_color_bar(struct drm_crtc *crtc, struct dentry *root);
int rockchip_drm_debugfs_add_regs_write(struct drm_crtc *crtc, struct dentry *root);
int rockchip_drm_debugfs_add_dclk_rate(struct drm_crtc *crtc, struct dentry *root);
#else
static inline int
rockchip_drm_add_dump_buffer(struct drm_crtc *crtc, struct dentry *root)
@@ -61,6 +62,12 @@ rockchip_drm_debugfs_add_regs_write(struct drm_crtc *crtc, struct dentry *root)
{
return 0;
}
static inline int
rockchip_drm_debugfs_add_dclk_rate(struct drm_crtc *crtc, struct dentry *root)
{
return 0;
}
#endif
#endif

1
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
View File

@@ -527,6 +527,7 @@ struct rockchip_crtc_funcs {
void (*crtc_output_post_enable)(struct drm_crtc *crtc, int intf);
void (*crtc_output_pre_disable)(struct drm_crtc *crtc, int intf);
int (*crtc_set_color_bar)(struct drm_crtc *crtc, enum rockchip_color_bar_mode mode);
unsigned long (*crtc_get_dclk_rate)(struct drm_crtc *crtc);
int (*set_aclk)(struct drm_crtc *crtc, enum rockchip_drm_vop_aclk_mode aclk_mode, struct dmcfreq_vop_info *vop_bw_info);
int (*get_crc)(struct drm_crtc *crtc);
void (*iommu_fault_handler)(struct drm_crtc *crtc, struct iommu_domain *iommu);

2
drivers/iio/adc/gpio_muxadc.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 Rockchip Electronics Co. Ltd.
* Copyright (c) 2018 Rockchip Electronics Co., Ltd.
*
* Author: Ziyuan Xu <xzy.xu@rock-chips.com>
*/

136
drivers/misc/rk628/rk628_dsi.c
View File

@@ -950,6 +950,17 @@ static void testif_write(struct rk628 *rk628, const struct rk628_dsi *dsi,
dev_info(rk628->dev, "monitor_data: 0x%x\n", monitor_data);
}
static u8 testif_read(struct rk628 *rk628, const struct rk628_dsi *dsi, u8 reg)
{
u8 value = 0;
testif_test_code_write(rk628, dsi, reg);
value = testif_get_data(rk628, dsi);
testif_test_data_write(rk628, dsi, value);
return value;
}
static void testif_set_timing(const struct rk628_dsi *dsi, u8 addr,
u8 max, u8 val)
{
@@ -961,6 +972,126 @@ static void testif_set_timing(const struct rk628_dsi *dsi, u8 addr,
testif_write(rk628, dsi, addr, (max + 1) | val);
}
static const struct {
char *name;
u8 reg;
u8 max;
} dphy_timing_table[] = {
{ "clk_lp", 0x60, 0x3f },
{ "clk_hs_prepare", 0x61, 0x7f },
{ "clk_hs_zero", 0x62, 0x3f },
{ "clk_hs_trail", 0x63, 0x7f },
{ "clk_post", 0x65, 0x0f },
{ "data_lp", 0x70, 0x3f },
{ "data_hs_prepare", 0x71, 0x7f },
{ "data_hs_zero", 0x72, 0x3f },
{ "data_hs_trail", 0x73, 0x7f },
};
static int rk628_dphy_timing_show(struct seq_file *s, void *v)
{
struct rk628 *rk628 = s->private;
u8 val;
seq_printf(s, "%-29sdphy0 dphy1\n", "");
for (int i = 0; i < ARRAY_SIZE(dphy_timing_table); i++) {
seq_printf(s, "%-15s(0x%02x ~ 0x%02x): ", dphy_timing_table[i].name, 0,
dphy_timing_table[i].max);
val = testif_read(rk628, &rk628->dsi0, dphy_timing_table[i].reg);
if (val & (dphy_timing_table[i].max + 1))
seq_printf(s, "0x%02x ", val & dphy_timing_table[i].max);
else
seq_puts(s, "auto ");
val = testif_read(rk628, &rk628->dsi1, dphy_timing_table[i].reg);
if (val & (dphy_timing_table[i].max + 1))
seq_printf(s, "0x%02x ", val & dphy_timing_table[i].max);
else
seq_puts(s, "auto ");
seq_puts(s, "\n");
}
seq_puts(s, "\n");
seq_puts(s, "example of modify single configuration:\n");
seq_puts(s, " echo dphy0.data_hs_prepare 0x40 > dphy_timing\n");
seq_puts(s, "example of modify multiple configurations:\n");
seq_puts(s, " echo dphy0 0x7 0x30 0x25 0x3c 0xf 0x7 0x40 0x9 0x40 > dphy_timing\n");
return 0;
}
static ssize_t rk628_dphy_timing_write(struct file *file, const char __user *buf, size_t count,
loff_t *ppos)
{
struct rk628 *rk628 = file->f_path.dentry->d_inode->i_private;
struct rk628_dsi *dsi;
char kbuf[51], *p;
u32 val;
int ret;
if (count >= sizeof(kbuf))
return -ENOSPC;
if (copy_from_user(kbuf, buf, count))
return -EFAULT;
kbuf[count] = '\0';
if (strstr(kbuf, "dphy0") == kbuf)
dsi = &rk628->dsi0;
else if (strstr(kbuf, "dphy1") == kbuf)
dsi = &rk628->dsi1;
else
return -EINVAL;
p = kbuf + 5;
if (*(p++) == '.') {
char name[51];
ret = sscanf(p, "%s %x", name, &val);
if (ret != 2)
return -EINVAL;
for (int i = 0; i < ARRAY_SIZE(dphy_timing_table); i++) {
if (strcmp(name, dphy_timing_table[i].name) == 0) {
testif_set_timing(dsi, dphy_timing_table[i].reg,
dphy_timing_table[i].max, val);
return count;
}
}
} else {
int i = 0;
while (i < ARRAY_SIZE(dphy_timing_table) && sscanf(p, "%x%n", &val, &ret) == 1) {
testif_set_timing(dsi, dphy_timing_table[i].reg,
dphy_timing_table[i].max, val);
i++;
p += ret;
}
return count;
}
return -EINVAL;
}
static int rk628_dphy_timing_open(struct inode *inode, struct file *file)
{
struct rk628 *rk628 = inode->i_private;
return single_open(file, rk628_dphy_timing_show, rk628);
}
static const struct file_operations rk628_dphy_timing_fops = {
.owner = THIS_MODULE,
.open = rk628_dphy_timing_open,
.read = seq_read,
.write = rk628_dphy_timing_write,
.llseek = seq_lseek,
.release = single_release,
};
static void mipi_dphy_set_timing(const struct rk628_dsi *dsi)
{
const struct {
@@ -1363,9 +1494,12 @@ static const struct file_operations rk628_dsi_color_bar_fops = {
void rk628_mipi_dsi_create_debugfs_file(struct rk628 *rk628)
{
if (rk628_output_is_dsi(rk628))
if (rk628_output_is_dsi(rk628)) {
debugfs_create_file("dsi_color_bar", 0600, rk628->debug_dir,
rk628, &rk628_dsi_color_bar_fops);
debugfs_create_file("dphy_timing", 0600, rk628->debug_dir,
rk628, &rk628_dphy_timing_fops);
}
}
void rk628_mipi_dsi_pre_enable(struct rk628 *rk628)

6
drivers/misc/rk628/rk628_hdmitx.c
View File

@@ -511,9 +511,9 @@ static int rk628_hdmi_config_video_timing(struct rk628_hdmi *hdmi,
value = mode->vsync_end - mode->vsync_start;
hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF);
hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e);
hdmi_writeb(hdmi, PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c);
hdmi_writeb(hdmi, PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01);
hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x02);
hdmi_writeb(hdmi, PHY_FEEDBACK_DIV_RATIO_LOW, 0x14);
hdmi_writeb(hdmi, PHY_FEEDBACK_DIV_RATIO_HIGH, 0x00);
return 0;
}

2
drivers/mtd/nand/bbt_store.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/

2
drivers/mtd/nand/raw/rockchip-nand-controller.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Rockchip NAND Flash controller driver.
* Copyright (C) 2020 Rockchip Inc.
* Copyright (C) 2020 Rockchip Electronics Co., Ltd.
* Author: Yifeng Zhao <yifeng.zhao@rock-chips.com>
*/

2
drivers/mtd/rknand/rknand_base.h
View File

@@ -2,7 +2,7 @@
/*
* linux/drivers/mtd/rknand/rknand_base.c
*
* Copyright (C) 2005-2009 Fuzhou Rockchip Electronics
* Copyright (C) 2005-2009 Rockchip Electronics Co., Ltd.
* ZYF <zyf@rock-chips.com>
*
*

2
drivers/mtd/rknand/rknand_base_ko.c
View File

@@ -2,7 +2,7 @@
/*
* linux/drivers/mtd/rknand/rknand_base.c
*
* Copyright (C) 2005-2009 Fuzhou Rockchip Electronics
* Copyright (C) 2005-2009 Rockchip Electronics Co., Ltd.
* ZYF <zyf@rock-chips.com>
*
*

2
drivers/net/ethernet/stmicro/stmmac/stmmac_uio.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/**
* Copyright 2023 ROCKCHIP
* Copyright 2023 Rockchip Electronics Co., Ltd.
*/
#include <linux/module.h>

2
drivers/net/phy/rk630phy.c
View File

@@ -3,7 +3,7 @@
*
* Driver for ROCKCHIP RK630 Ethernet PHYs
*
* Copyright (c) 2020, Rockchip Electronics Co., Ltd
* Copyright (c) 2020, Rockchip Electronics Co., Ltd.
*
* David Wu <david.wu@rock-chips.com>
*

12
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
View File

@@ -200,7 +200,7 @@ static const struct rockchip_p3phy_ops rk3588_ops = {
.phy_calibrate = rockchip_p3phy_rk3588_calibrate,
};
static int rochchip_p3phy_init(struct phy *phy)
static int rockchip_p3phy_init(struct phy *phy)
{
struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
int ret;
@@ -223,7 +223,7 @@ static int rochchip_p3phy_init(struct phy *phy)
return ret;
}
static int rochchip_p3phy_exit(struct phy *phy)
static int rockchip_p3phy_exit(struct phy *phy)
{
struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
@@ -232,9 +232,9 @@ static int rochchip_p3phy_exit(struct phy *phy)
return 0;
}
static const struct phy_ops rochchip_p3phy_ops = {
.init = rochchip_p3phy_init,
.exit = rochchip_p3phy_exit,
static const struct phy_ops rockchip_p3phy_ops = {
.init = rockchip_p3phy_init,
.exit = rockchip_p3phy_exit,
.set_mode = rockchip_p3phy_set_mode,
.owner = THIS_MODULE,
};
@@ -294,7 +294,7 @@ static int rockchip_p3phy_probe(struct platform_device *pdev)
(reg << 16) | reg);
};
priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops);
if (IS_ERR(priv->phy)) {
dev_err(dev, "failed to create combphy\n");
return PTR_ERR(priv->phy);

2
drivers/pinctrl/pinctrl-max96745.c
View File

@@ -2,7 +2,7 @@
/*
* Maxim MAX96745 pin control driver
*
* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
#include <linux/module.h>

2
drivers/pinctrl/pinctrl-max96755f.c
View File

@@ -2,7 +2,7 @@
/*
* Maxim max96755f pin control driver.
*
* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
#include <linux/module.h>

2
drivers/pinctrl/pinctrl-rockchip.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
*
* Copyright (c) 2013 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>

2
drivers/power/ec_battery.c
View File

@@ -1,7 +1,7 @@
/*
* ec battery driver
*
* Copyright (C) 2016 Rockchip Electronics Co., Ltd
* Copyright (C) 2016 Rockchip Electronics Co., Ltd.
* Shunqing Chen <csq@rock-chips.com>
*
* This program is free software; you can redistribute it and/or modify it

2
drivers/power/supply/cw2015_battery.c
View File

@@ -2,7 +2,7 @@
/*
* Fuel gauge driver for CellWise 2013 / 2015
*
* Copyright (C) 2012, RockChip
* Copyright (C) 2012, Rockchip Electronics Co., Ltd.
* Copyright (C) 2020, Tobias Schramm
*
* Authors: xuhuicong <xhc@rock-chips.com>

2
drivers/power/supply/rk817_charger.c
View File

@@ -1,7 +1,7 @@
/*
* rk817 charger driver
*
* Copyright (C) 2018 Rockchip Electronics Co., Ltd
* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
* xsf <xsf@rock-chips.com>
*
* This program is free software; you can redistribute it and/or modify it

2
drivers/pwm/pwm-rockchip-i2s.c
View File

@@ -3,7 +3,7 @@
/*
* PWM-I2S driver for Rockchip SoCs
*
* Copyright (c) 2018 Rockchip Electronics Co. Ltd.
* Copyright (c) 2018 Rockchip Electronics Co., Ltd.
*/
#include <linux/clk.h>

2
drivers/pwm/pwm-rockchip.c
View File

@@ -3,7 +3,7 @@
* PWM driver for Rockchip SoCs
*
* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
* Copyright (C) 2014 ROCKCHIP, Inc.
* Copyright (C) 2014 Rockchip Electronics Co., Ltd.
*/
#include <linux/clk.h>

2
drivers/rtc/rtc-hym8563.c
View File

@@ -6,7 +6,7 @@
* Author: Heiko Stuebner <heiko@sntech.de>
*
* based on rtc-HYM8563
* Copyright (C) 2010 ROCKCHIP, Inc.
* Copyright (C) 2010 Rockchip Electronics Co., Ltd.
*/
#include <linux/module.h>

9
drivers/soc/rockchip/rk_dmabuf_procfs.c
View File

@@ -10,6 +10,7 @@
#include <linux/scatterlist.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/dma-resv.h>
#define K(size) ((unsigned long)((size) >> 10))
static struct device *dmabuf_dev;
@@ -59,6 +60,8 @@ static void rk_dmabuf_dump_sgt(const struct dma_buf *dmabuf, void *private)
phys_addr_t end, len;
int i;
dma_resv_lock(dmabuf->resv, NULL);
list_for_each_entry_safe(a, t, &dmabuf->attachments, node) {
if (!a->sgt)
continue;
@@ -76,8 +79,12 @@ static void rk_dmabuf_dump_sgt(const struct dma_buf *dmabuf, void *private)
(len >> 10) ? (K(len)) : (unsigned long)len,
(len >> 10) ? "KiB" : "Bytes");
}
dma_resv_unlock(dmabuf->resv);
return;
}
dma_resv_unlock(dmabuf->resv);
/* Try to attach and map the dmabufs without sgt. */
if (IS_ENABLED(CONFIG_RK_DMABUF_DEBUG_ADVANCED)) {
struct dma_buf *dbuf = (struct dma_buf *)dmabuf;
@@ -105,9 +112,11 @@ static int rk_dmabuf_cb3(const struct dma_buf *dmabuf, void *private)
seq_printf(s, "%px %-16.16s %-16.16s %10lu KiB",
dmabuf, dmabuf->name,
dmabuf->exp_name, K(dmabuf->size));
dma_resv_lock(dmabuf->resv, NULL);
list_for_each_entry_safe(a, t, &dmabuf->attachments, node) {
seq_printf(s, " %s", dev_name(a->dev));
}
dma_resv_unlock(dmabuf->resv);
seq_puts(s, "\n");
return 0;

2
drivers/spi/spi-rockchip-sfc.c
View File

@@ -2,7 +2,7 @@
/*
* Rockchip Serial Flash Controller Driver
*
* Copyright (c) 2017-2021, Rockchip Inc.
* Copyright (c) 2017-2021, Rockchip Electronics Co., Ltd.
* Author: Shawn Lin <shawn.lin@rock-chips.com>
* Chris Morgan <macroalpha82@gmail.com>
* Jon Lin <Jon.lin@rock-chips.com>

2
drivers/spi/spi-rockchip-slave.c
View File

@@ -2,7 +2,7 @@
/*
* Rockchip SPI Slave Controller Driver
*
* Copyright (c) 2023, Rockchip Inc.
* Copyright (c) 2023, Rockchip Electronics Co., Ltd.
* Author: Jon Lin <Jon.lin@rock-chips.com>
*/

2
drivers/thermal/rk_virtual_thermal.c
View File

@@ -1,7 +1,7 @@
/*
* rk virtual tsadc driver
*
* Copyright (C) 2017 Rockchip Electronics Co., Ltd
* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
* Author: Rocky Hao <rocky.hao@rock-chips.com>
*
* This program is free software; you can redistribute it and/or modify it

2
drivers/usb/typec/tcpm/tcpci_et7303.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2022 Rockchip Co.,Ltd.
* Copyright (C) 2022 Rockchip Electronics Co., Ltd.
* Author: Wang Jie <dave.wang@rock-chips.com>
*
* Etek ET7303 Type-C Chip Driver

2
drivers/usb/typec/tcpm/tcpci_husb311.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Rockchip Co.,Ltd.
* Copyright (C) 2021 Rockchip Electronics Co., Ltd.
* Author: Wang Jie <dave.wang@rock-chips.com>
*
* Hynetek Husb311 Type-C Chip Driver

2
drivers/video/rockchip/rga/rga_drv.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2012 ROCKCHIP, Inc.
* Copyright (C) 2012 Rockchip Electronics Co., Ltd.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and

2
drivers/video/rockchip/rga2/rga2_drv.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2012 ROCKCHIP, Inc.
* Copyright (C) 2012 Rockchip Electronics Co., Ltd.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and

2
drivers/video/rockchip/vtunnel/rkvtunnel.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
#ifndef __ROCKCHIP_VIDEO_TUNNEL_H__
#define __ROCKCHIP_VIDEO_TUNNEL_H__

3
include/dt-bindings/clock/rockchip,rk3506-cru.h
View File

@@ -280,8 +280,9 @@
#define CLK_WIFI_OUT 281
#define CLK_V0PLL_REF 282
#define CLK_V1PLL_REF 283
#define CLK_32K_FRAC_MUX 284
#define CLK_NR_CLKS (CLK_V1PLL_REF + 1)
#define CLK_NR_CLKS (CLK_32K_FRAC_MUX + 1)
/* soft-reset indices */

2
include/dt-bindings/soc/rockchip-csu.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023 Rockchip Electronics Co. Ltd.
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
* Author: Finley Xiao <finley.xiao@rock-chips.com>
*/

2
include/dt-bindings/soc/rockchip-system-status.h
View File

@@ -1,6 +1,6 @@
/*
*
* Copyright (C) 2017 ROCKCHIP, Inc.
* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and

2
include/linux/clk/rockchip.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
*/
#ifndef __LINUX_CLK_ROCKCHIP_H_

2
include/linux/dma-buf-cache.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
#ifndef _LINUX_DMA_BUF_CACHE_H
#define _LINUX_DMA_BUF_CACHE_H

2
include/linux/mfd/max96745.h
View File

@@ -2,7 +2,7 @@
/*
* Defining registers address and its bit definitions of MAX96745
*
* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
#ifndef _MFD_MAX96745_H_

2
include/linux/mfd/max96755f.h
View File

@@ -2,7 +2,7 @@
/*
* Defining registers address and its bit definitions of MAX96752F
*
* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
#ifndef _MFD_MAX96755F_H_

2
include/linux/mfd/rk618.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017 Rockchip Electronics Co. Ltd.
* Copyright (c) 2017 Rockchip Electronics Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

2
include/linux/mfd/rk630.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
*
* Author: Algea Cao <algea.cao@rock-chips.com>
*/

2
include/linux/mtd/bbt_store.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/

2
include/linux/platform_data/spi-rockchip.h
View File

@@ -1,6 +1,6 @@
/* include/linux/platform_data/spi-rockchip.h
*
* Copyright (C) 2014 Rockchip Electronics Ltd.
* Copyright (C) 2014 Rockchip Electronics Co., Ltd.
* luowei <lw@rock-chips.com>
*
* This program is free software; you can redistribute it and/or modify

2
include/linux/power/cw2015_battery.h
View File

@@ -1,7 +1,7 @@
/*
* Fuel gauge driver for CellWise 2013 / 2015
*
* Copyright (C) 2012, RockChip
* Copyright (C) 2012, Rockchip Electronics Co., Ltd.
*
* Authors: xuhuicong <xhc@rock-chips.com>
*

2
include/linux/rk-dma-heap.h
View File

@@ -4,7 +4,7 @@
*
* Copyright (C) 2011 Google, Inc.
* Copyright (C) 2019 Linaro Ltd.
* Copyright (C) 2022 Rockchip Electronics Co. Ltd.
* Copyright (C) 2022 Rockchip Electronics Co., Ltd.
* Author: Simon Xue <xxm@rock-chips.com>
*/

2
include/linux/rk_hdmirx_class.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
* Author: Dingxian Wen <shawn.wen@rock-chips.com>
*/

2
include/linux/rockchip-panel-notifier.h
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@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2024 Rockchip Electronics Co. Ltd.
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
* Author: Zhibin Huang <zhibin.huang@rock-chips.com>
*/

2
include/linux/rockchip/cpu.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017 Rockchip Electronics Co. Ltd.
* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
include/linux/sensor-dev.h
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@@ -1,6 +1,6 @@
/* include/linux/sensor-dev.h - sensor header file
*
* Copyright (C) 2012-2015 ROCKCHIP.
* Copyright (C) 2012-2015 Rockchip Electronics Co., Ltd.
* Author: luowei <lw@rock-chips.com>
*
* This software is licensed under the terms of the GNU General Public

2
include/linux/soc/rockchip/rockchip_decompress.h
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@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (c) 2020 Rockchip Electronics Co., Ltd */
/* Copyright (c) 2020 Rockchip Electronics Co., Ltd. */
#ifndef _ROCKCHIP_DECOMPRESS
#define _ROCKCHIP_DECOMPRESS

2
include/linux/soc/rockchip/rockchip_thunderboot_crypto.h
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@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (c) 2021 Rockchip Electronics Co., Ltd */
/* Copyright (c) 2021 Rockchip Electronics Co., Ltd. */
#ifndef _ROCKCHIP_THUNDERBOOT_CRYPTO_
#define _ROCKCHIP_THUNDERBOOT_CRYPTO_

2
include/linux/soc/rockchip/rockchip_thunderboot_service.h
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@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (c) 2022 Rockchip Electronics Co., Ltd */
/* Copyright (c) 2022 Rockchip Electronics Co., Ltd. */
#ifndef _ROCKCHIP_THUNDERBOOT_SERVICE_H
#define _ROCKCHIP_THUNDERBOOT_SERVICE_H

2
include/misc/rk_scr_api.h
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@@ -1,7 +1,7 @@
/*
* Driver for Rockchip Smart Card Reader Controller
*
* Copyright (C) 2012-2016 ROCKCHIP, Inc.
* Copyright (C) 2012-2016 Rockchip Electronics Co., Ltd.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and

2
include/uapi/linux/rk-dma-heap.h
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@@ -4,7 +4,7 @@
*
* Copyright (C) 2011 Google, Inc.
* Copyright (C) 2019 Linaro Ltd.
* Copyright (C) 2022 Rockchip Electronics Co. Ltd.
* Copyright (C) 2022 Rockchip Electronics Co., Ltd.
* Author: Simon Xue <xxm@rock-chips.com>
*/
#ifndef _UAPI_LINUX_DMABUF_POOL_H

2
include/uapi/misc/dw_hdcp2.h
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@@ -2,7 +2,7 @@
/*
* Rockchip HDCP Host Library driver
*
* Copyright (C) 2022 Rockchip Electronics Co., Ltd
* Copyright (C) 2022 Rockchip Electronics Co., Ltd.
*/
#ifndef _DW_HDCP_HOST_LIB_DRIVER_LINUX_IF_H_

2
include/uapi/misc/rkflash_vendor_storage.h
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@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT) */
/* Copyright (c) 2023 Rockchip Electronics Co., Ltd */
/* Copyright (c) 2023 Rockchip Electronics Co., Ltd. */
#ifndef _RKFLASH_VENDOR_STORAGE
#define _RKFLASH_VENDOR_STORAGE