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Merge commit '29918d51d62ef05126f3ff2ba1a91c66966e55fe'

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* commit '29918d51d62ef05126f3ff2ba1a91c66966e55fe':
  clk: rockchip: rk3506: Add ROCKCHIP_PLL_ALLOW_POWER_DOWN flag for v1pll
  clk: rockchip: rk3506: Add 750MHz for cpu
  drm/bridge: synopsys: dw-hdmi-qp: Fixed ddc write heap corruption
  drm/rockchip: vop2: enable rb swap for MEDIA_BUS_FMT_BGR888_1X24
  drm/rockchip: vop: set dclk inverted by default for bt1120/bt656/rgb on rk3506

Change-Id: Ibd797a190299f7bc12955fb43b41672dba29c029
This commit is contained in:
Tao Huang
2024-10-12 20:16:54 +08:00
parent 52b27dd56a 29918d51d6
commit b75553cea9
4 changed files with 16 additions and 7 deletions
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4
drivers/clk/rockchip/clk-rk3506.c
View File

@@ -100,6 +100,7 @@ static struct rockchip_cpuclk_rate_table rk3506_cpuclk_rates[] __initdata = {
RK3506_CPUCLK_RATE(1008000000, 1, 7),
RK3506_CPUCLK_RATE(903168000, 1, 7),
RK3506_CPUCLK_RATE(800000000, 1, 6),
RK3506_CPUCLK_RATE(750000000, 1, 5),
RK3506_CPUCLK_RATE(589824000, 1, 4),
RK3506_CPUCLK_RATE(400000000, 1, 3),
RK3506_CPUCLK_RATE(200000000, 1, 1),
@@ -160,7 +161,8 @@ static struct rockchip_pll_clock rk3506_pll_clks[] __initdata = {
RK3506_MODE_CON, 2, 0, 0, rk3506_pll_rates),
[v1pll] = PLL(pll_rk3328, PLL_V1PLL, "v1pll", mux_pll_p,
0, RK3506_PLL_CON(16),
RK3506_MODE_CON, 4, 1, 0, rk3506_pll_rates),
RK3506_MODE_CON, 4, 1,
ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3506_pll_rates),
};
static struct rockchip_clk_branch rk3506_armclk __initdata =

3
drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
View File

@@ -1158,7 +1158,7 @@ static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi,
reinit_completion(&i2c->cmp);
hdmi_writel(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3);
hdmi_writel(hdmi, *buf, I2CM_INTERFACE_WRDATA_0_3);
hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR,
I2CM_INTERFACE_CONTROL0);
hdmi_modb(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK,
@@ -1183,6 +1183,7 @@ static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi,
continue;
}
/* write success */
buf++;
break;
}
hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);

13
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View File

@@ -3597,10 +3597,6 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
}
dclk_inv = (s->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0;
/* For improving signal quality, dclk need to be inverted by default on rv1106. */
if (vop->version == VOP_VERSION_RV1106)
dclk_inv = !dclk_inv;
VOP_CTRL_SET(vop, dclk_pol, dclk_inv);
val = (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
0 : BIT(HSYNC_POSITIVE);
@@ -3616,6 +3612,15 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
switch (s->output_type) {
case DRM_MODE_CONNECTOR_DPI:
/*
* In order to ensure that the data is sampled along the rising
* edge without flag DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, dclk of
* bt1120/bt656/rgb need to be inverted by default on rv1106 and
* rk3506.
*/
if (vop->version == VOP_VERSION_RV1106 || vop->version == VOP_VERSION_RK3506)
dclk_inv = !dclk_inv;
fallthrough;
case DRM_MODE_CONNECTOR_LVDS:
VOP_CTRL_SET(vop, rgb_en, 1);
VOP_CTRL_SET(vop, rgb_pin_pol, val);

3
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -2450,7 +2450,8 @@ static bool vop3_output_rb_swap(struct rockchip_crtc_state *vcstate)
* The default component order of serial rgb3x8 formats
* is BGR. So it is needed to enable RB swap.
*/
if (bus_format == MEDIA_BUS_FMT_RGB888_3X8 ||
if (bus_format == MEDIA_BUS_FMT_BGR888_1X24 ||
bus_format == MEDIA_BUS_FMT_RGB888_3X8 ||
bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8)
return true;
else