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arm64: dts: rockchip: Change rk618 clkin rate to 11.2896MHz

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Change-Id: I5d4b00855d29bc4f2ccf6754eb191e70f1632f51
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
2019-08-13 15:27:52 +08:00
committed by Tao Huang
parent 7e2c9c679c
commit c771f313d2
7 changed files with 9 additions and 9 deletions
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2
arch/arm64/boot/dts/rockchip/px30-ad-r35-mb-rk618-dual-lvds.dts
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@@ -69,7 +69,7 @@
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "clkin";
assigned-clocks = <&cru SCLK_I2S1_OUT>;
assigned-clock-rates = <12000000>;
assigned-clock-rates = <11289600>;
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
status = "okay";

2
arch/arm64/boot/dts/rockchip/px30-ad-r35-mb-rk618-hdmi-lvds.dts
View File

@@ -70,7 +70,7 @@
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "clkin";
assigned-clocks = <&cru SCLK_I2S1_OUT>;
assigned-clock-rates = <12000000>;
assigned-clock-rates = <11289600>;
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
status = "okay";

2
arch/arm64/boot/dts/rockchip/px30-ad-r35-mb-rk618-hdmi.dts
View File

@@ -22,7 +22,7 @@
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "clkin";
assigned-clocks = <&cru SCLK_I2S1_OUT>;
assigned-clock-rates = <12000000>;
assigned-clock-rates = <11289600>;
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
status = "okay";

2
arch/arm64/boot/dts/rockchip/px30-evb-ext-rk618.dtsi
View File

@@ -31,7 +31,7 @@
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "clkin";
assigned-clocks = <&cru SCLK_I2S1_OUT>;
assigned-clock-rates = <12000000>;
assigned-clock-rates = <11289600>;
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
status = "okay";

4
arch/arm64/boot/dts/rockchip/rk3326-w7-icn6211-rk618-hdmi-rgb.dts
View File

@@ -98,7 +98,7 @@
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "clkin";
assigned-clocks = <&cru SCLK_I2S1_OUT>;
assigned-clock-rates = <12000000>;
assigned-clock-rates = <11289600>;
reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
status = "okay";
@@ -113,7 +113,7 @@
<&clock CODEC_CLK>,
<&clock DITHER_CLK>;
assigned-clock-parents = <&cru SCLK_I2S1_OUT>,
<&cru SCLK_I2S1_OUT>,
<&clock LCDC0_CLK>,
<&clock SCALER_PLL_CLK>,
<&clock VIF_PLL_CLK>,
<&cru SCLK_I2S1_OUT>,

4
arch/arm64/boot/dts/rockchip/rk3326-w7-icn6211-rk618-hdmi.dts
View File

@@ -58,7 +58,7 @@
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "clkin";
assigned-clocks = <&cru SCLK_I2S1_OUT>;
assigned-clock-rates = <12000000>;
assigned-clock-rates = <11289600>;
reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
status = "okay";
@@ -73,7 +73,7 @@
<&clock CODEC_CLK>,
<&clock DITHER_CLK>;
assigned-clock-parents = <&cru SCLK_I2S1_OUT>,
<&cru SCLK_I2S1_OUT>,
<&clock LCDC0_CLK>,
<&clock SCALER_PLL_CLK>,
<&clock VIF_PLL_CLK>,
<&cru SCLK_I2S1_OUT>,

2
arch/arm64/boot/dts/rockchip/rk3368-sziauto-rk618.dts
View File

@@ -250,7 +250,7 @@
clocks = <&cru SCLK_I2S_8CH_OUT>;
clock-names = "clkin";
assigned-clocks = <&cru SCLK_I2S_8CH_OUT>;
assigned-clock-rates = <12000000>;
assigned-clock-rates = <11289600>;
reset-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
status = "okay";