clk: axg fix_pll use frac mode

PD#154040: axg fix_pll enable frac mode describe

Change-Id: I1223b5710687a2e9902d953fd7c8eac9c8574f4d
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>

drivers/amlogic/clk/axg/axg.c

@@ -60,6 +60,11 @@ static struct meson_clk_pll axg_fixed_pll = {
 		.shift   = 16,
 		.width   = 2,
 	},
+	.frac = {
+		.reg_off = HHI_MPLL_CNTL2,
+		.shift   = 0,
+		.width   = 12,
+	},
 	.lock = &clk_lock,
 	.hw.init = &(struct clk_init_data){
 		.name = "fixed_pll",