shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-08 20:07:46 +09:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: rockchip: rk3326-w7: set VIF_PLL and SCL_PLL clock parents to LCDC0_CLK

Browse Source 
Change-Id: I71fce70e464771278719affb8f2573d0dbda1a27
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
2019-05-29 15:40:13 +08:00
committed by Tao Huang
parent c9aee8efb3
commit d883eb7e3c
1 changed files with 2 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm64/boot/dts/rockchip/rk3326-w7-icn6211-rk618-hdmi-rgb.dts
View File

@@ -97,8 +97,6 @@
pinctrl-0 = <&i2s1_2ch_mclk>;
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "clkin";
assigned-clocks = <&cru SCLK_I2S1_OUT>;
assigned-clock-rates = <12000000>;
reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
status = "okay";
@@ -112,8 +110,8 @@
<&clock VIF0_PRE_CLK>,
<&clock CODEC_CLK>,
<&clock DITHER_CLK>;
assigned-clock-parents = <&cru SCLK_I2S1_OUT>,
<&cru SCLK_I2S1_OUT>,
assigned-clock-parents = <&clock LCDC0_CLK>,
<&clock LCDC0_CLK>,
<&clock SCALER_PLL_CLK>,
<&clock VIF_PLL_CLK>,
<&cru SCLK_I2S1_OUT>,