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clk: rockchip: rk3588: support npll/aupll/v0pll power down by auto

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Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ida2f113f6989eb9db9d97522514299d4660bbb69
This commit is contained in:
Elaine Zhang
2021-11-22 09:58:41 +08:00
committed by Tao Huang
parent 4074c7cc38
commit dde2f927c2
2 changed files with 7 additions and 6 deletions
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1
drivers/clk/rockchip/clk-pll.c
View File

@@ -1674,6 +1674,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
init.ops = &rockchip_rk3588_pll_clk_norate_ops;
else
init.ops = &rockchip_rk3588_pll_clk_ops;
init.flags = flags;
break;
default:
pr_warn("%s: Unknown pll type for pll clk %s\n",

12
drivers/clk/rockchip/clk-rk3588.c
View File

@@ -637,13 +637,13 @@ static struct rockchip_clk_branch rk3588_hdmirx_aud_fracmux __initdata =
static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = {
[b0pll] = PLL(pll_rk3588_core, PLL_B0PLL, "b0pll", mux_pll_p,
0, RK3588_B0_PLL_CON(0),
CLK_IGNORE_UNUSED, RK3588_B0_PLL_CON(0),
RK3588_BIGCORE0_CLKSEL_CON(0), 6, 15, 0, rk3588_pll_rates),
[b1pll] = PLL(pll_rk3588_core, PLL_B1PLL, "b1pll", mux_pll_p,
0, RK3588_B1_PLL_CON(8),
CLK_IGNORE_UNUSED, RK3588_B1_PLL_CON(8),
RK3588_BIGCORE1_CLKSEL_CON(0), 6, 15, 0, rk3588_pll_rates),
[lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p,
0, RK3588_LPLL_CON(16),
CLK_IGNORE_UNUSED, RK3588_LPLL_CON(16),
RK3588_DSU_CLKSEL_CON(5), 14, 15, 0, rk3588_pll_rates),
[v0pll] = PLL(pll_rk3588, PLL_V0PLL, "v0pll", mux_pll_p,
0, RK3588_PLL_CON(88),
@@ -652,16 +652,16 @@ static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = {
0, RK3588_PLL_CON(96),
RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates),
[cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p,
0, RK3588_PLL_CON(104),
CLK_IGNORE_UNUSED, RK3588_PLL_CON(104),
RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates),
[gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p,
0, RK3588_PLL_CON(112),
CLK_IGNORE_UNUSED, RK3588_PLL_CON(112),
RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates),
[npll] = PLL(pll_rk3588, PLL_NPLL, "npll", mux_pll_p,
0, RK3588_PLL_CON(120),
RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
[ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p,
0, RK3588_PMU_PLL_CON(128),
CLK_IGNORE_UNUSED, RK3588_PMU_PLL_CON(128),
RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
};