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clk: sm1: add sm1 dsu clk notify for change dsu freq [1/1]

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PD#SWPL-8145

Problem:
dsu clk can't change freq

Solution:
add sm1 dsu clk notify

Verify:
sm1_skt

Change-Id: If3ecf1066b49c07e6af69ce342956cb0469a5f87
Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
Signed-off-by: Hong Guo <hong.guo@amlogic.com>
This commit is contained in:
Shunzhou Jiang
2019-05-14 09:47:43 +08:00
committed by Luke Go
parent 1ba443cfdc
commit e56c051873
2 changed files with 50 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
arch/arm/boot/dts/amlogic/mesonsm1.dtsi
View File

@@ -58,10 +58,14 @@
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_PRE_CLK>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
cpu-supply = <&vddcpu0>;
voltage-tolerance = <0>;
@@ -76,10 +80,14 @@
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_PRE_CLK>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
cpu-supply = <&vddcpu0>;
voltage-tolerance = <0>;
@@ -94,10 +102,14 @@
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_PRE_CLK>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
cpu-supply = <&vddcpu0>;
voltage-tolerance = <0>;
@@ -112,10 +124,14 @@
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_PRE_CLK>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
cpu-supply = <&vddcpu0>;
voltage-tolerance = <0>;
@@ -762,6 +778,7 @@
compatible = "amlogic,sm1-clkc-2";
#clock-cells = <1>;
reg = <0x0 0x3dc>;
own-dsu-clk;
};
};/* end of hiubus*/

33
arch/arm64/boot/dts/amlogic/mesonsm1.dtsi
View File

@@ -58,10 +58,14 @@
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_PRE_CLK>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
cpu-supply = <&vddcpu0>;
voltage-tolerance = <0>;
@@ -76,10 +80,14 @@
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_PRE_CLK>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
cpu-supply = <&vddcpu0>;
voltage-tolerance = <0>;
@@ -94,10 +102,14 @@
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_PRE_CLK>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
cpu-supply = <&vddcpu0>;
voltage-tolerance = <0>;
@@ -112,10 +124,14 @@
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_PRE_CLK>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
cpu-supply = <&vddcpu0>;
voltage-tolerance = <0>;
@@ -762,6 +778,7 @@
compatible = "amlogic,sm1-clkc-2";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0x3dc>;
own-dsu-clk;
};
};/* end of hiubus*/