shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 03:15:31 +09:00
Code Issues Packages Projects Releases Wiki Activity

clk: rockchip: rk3288: add ddrc clock support

Browse Source 
Add a ddrc clock into clk branches, so we can do ddr frequency
scaling on rk3288 platform in future.

Change-Id: Ia6c93e5ce82fa30475eddf051bc9ea2512b0cc07
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Finley Xiao
2017-04-06 11:40:01 +08:00
committed by Tao Huang
parent 2550716315
commit e9b2f6ce99
2 changed files with 5 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/clk/rockchip/clk-rk3288.c
View File

@@ -329,8 +329,11 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(0), 8, GFLAGS),
GATE(0, "gpll_ddr", "gpll", 0,
GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
RK3288_CLKSEL_CON(26), 2, 1, 0, 0,
ROCKCHIP_DDRCLK_SIP),
COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
DFLAGS | CLK_DIVIDER_POWER_OF_TWO),

1
include/dt-bindings/clock/rk3288-cru.h
View File

@@ -80,6 +80,7 @@
#define SCLK_CRYPTO 125
#define SCLK_MIPIDSI_24M 126
#define SCLK_VIP_OUT 127
#define SCLK_DDRCLK 128
#define SCLK_MAC 151
#define SCLK_MACREF_OUT 152