RKCE has redesigned the operational flow of CRYPTO to implement
pipelined computing. Using the standard crypto engine framework on
the driver can greatly simplify the logic of the code.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: Ia6f5e2321ab4c7ae01d33cbd30a222bf32706ab4
Support 4lane MIPI interface, 1.5Gbps/lane
Max output resolution is 1920x1080@60fps
Change-Id: I6b99b9d42aefd6f07a2bc49c9bb1696d712ed1fa
Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com>
RV1126B VOP has a writeback with max 1920 x 1080 output.
Writeback work as a connector in drm system.
Change-Id: I550601e480630a841c9abfadb9eda2204c074592
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
RV1126B supports calculating the exact dclk from the known aclk rate.
Change-Id: I92539f34eda514a5f35ce53ece98109dac888d6c
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
RV1126B support horizontial and vertical color bar.
Change-Id: Idf4fe9d125585286b928f4728b0567ea4c20aa2e
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
VOP on RV1126B support 2 win, max output resolution 1920x1080P60:
Win0 MAX 1920x1080, support line YUV/RGB
Win2 MAX 1920x1080, support RGB
RV1126B VOP also supports write back feature, max resolution 1920x1080.
Change-Id: I07376ec32e5200f29038b5bdcacc0ac31bd7e915
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
This driver is modified to support RV1126B SoCs.
Change-Id: I9f2c09f229e933f68f37af179ef8d6c27bc09a41
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
1.Support data shift.
2.Move the hpf after cic filter.
3.Separate the gain control.
Change-Id: I092360fad0945084c3b44f3a31be6ee67371755a
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
e.g. mask the right channel for play and rec
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <32>;
dai-tdm-slot-tx-mask = <0 1>;
dai-tdm-slot-rx-mask = <0 1>;
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Id359876f47916417ee6be9e607b05b79665cd9bf
Add the clock tree definition for the new RV1126B SoC.
Change-Id: Id03fb5d02c59fc2f4a55e0a9b7a98692a049d6bf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add the dt-bindings header for the rv1126b, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rv1126b.
Change-Id: I565399bb3a338453c6f2f3ac5d79775ad2be9481
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
All hdmi 2.1 contents in the edid are saved in this
struct.
Change-Id: I2400fb9fe77163667419677ca3f55e88d795d2be
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
The HDMI spec 10.3.2 talks about SCDS, Sink Capability Data
Structure, exposed via HF-VSDB or HF-SCDB. The actual content
of the them is same. So it needs only one parse function.
Change-Id: I61459b6d21d7e0666c1561bb2ad41729e0d00a49
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
When assign the vp dclk parent as hdmi phy pll in dts. The
vp dclk parent should get by clk_get_parent. The vp.dclk_parent
is not the real parent.
Change-Id: I4b1ba1e1b46e2f5db323069402c4b322ba4a836f
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
1.Determine whether to enable dsc based on the current resolution
and color format.
2.Determine the dsc format of the output according to the
capability of sink.
Change-Id: If7a1c88ea1b6ec0208c9dc9d91a56376ff656707
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
When the dsc bpp is less than 9, hdmi output will flash on TV.
It is speculated that the reason is that pixel rate of sink
decoding is not enough.
Taking 8bpp as an example, dsc clk needs to be 1/3 of the input
clk.the theoretical calculation of DEN compression 1/3, at this
time, the clk of vop dsc to hdmi tx can be reduced to about 260M
to meet the 8bpp transmission.
RK3588 dsc clk only supports 1/2 frequency division, so dsc clk
is 1/2 input clk, which needs to increase blank, which is
equivalent to compressing the absolute DEN time. TV is likely to
decode at a decoding rate of around 260M. DEN absolute time
shortening results in abnormal TV decoding.
So the value of hblank needs to be reduced when bpp is below 9.
The measurement can be displayed normally on TV, but reducing
the hblank will result in non-standard timing of the hdmi output.
This may cause compatibility issues and hdmi cts certification
may fail.
Change-Id: I6cd7890c62980c29322c437b20fb048fe0acbae3
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
In order to cover more application scenarios, when the crtc changes,
the old output_if should be cleared, rather than when the flag
&drm_crtc_state.active_changed is set to 1.
In addition, it would be more reasonable to name new crtc to 'new_crtc'
rather than 'crtc'.
Change-Id: I6821e85b0b6f1152cea3057ebb6f3ec9b821ebee
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
In order to cover more application scenarios, when the crtc changes,
the old output_if should be cleared, rather than when the flag
&drm_crtc_state.active_changed is set to 1.
In addition, it would be more reasonable to name new crtc to 'new_crtc'
rather than 'crtc'.
Change-Id: I5376c44eb5deab75acdbae95782cc5de2e2757d5
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Replace the rockchip_dp_drm_get_new_crtc() by the existing function
drm_atomic_get_new_crtc_for_encoder(), which defined in common Rockchip
DRM driver file 'drivers/gpu/drm/rockchip/rockchip_drm_drv.c'.
Change-Id: I011dc70b5e7e927a201c80cc8ecb15dbef446631
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
struct mutex commit_lock is only used by kernel 4.19,
use ovl_lock now.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Id7eb81fac31026956eeb9b8799b7d8281e4de4c2
For some platforms, such as RK3576, use the win scale instead
of the post scale to configure overscan parameters, because the
sharp/post scale/split functions are mutually exclusice.
Change-Id: If422749ed8defc553924f14f24ab173913b2dcad
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
