The SD card on the SoPine SoM module is somewhat concealed, so was
originally defined as "non-removable".
However there is a working card-detect pin (tested on two different
SoM versions), and in certain SoM base boards it might be actually
accessible at runtime.
Also the Pine64-LTS shares the SoPine base .dtsi, so inherited the
non-removable flag, even though the SD card slot is perfectly accessible
and usable there. (It turns out that just *my* board has a broken card
detect switch, so I originally thought CD wouldn't work on the LTS.)
Drop the "non-removable" flag to describe the SD card slot properly.
Fixes: c3904a2698 ("arm64: allwinner: a64: add DTSI file for SoPine SoM")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210113152630.28810-5-andre.przywara@arm.com
In recent Allwinner SoCs the first USB host controller (HCI0) shares
the first PHY with the MUSB controller. Probably to make this sharing
work, we were avoiding to declare this in the DT. This has two
shortcomings:
- U-Boot (which uses the same .dts) cannot use this port in host mode
without a PHY linked, so we were loosing one USB port there.
- It requires the MUSB driver to be enabled and loaded, although we
don't actually use it.
To avoid those issues, let's add this PHY link to the H6 .dtsi file.
After all PHY port 0 *is* connected to HCI0, so we should describe
it as this.
This makes it work in U-Boot, also improves compatiblity when no MUSB
driver is loaded (for instance in distribution installers).
Fixes: eabb3d424b ("arm64: dts: allwinner: h6: add USB2-related device nodes")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210113152630.28810-3-andre.przywara@arm.com
In recent Allwinner SoCs the first USB host controller (HCI0) shares
the first PHY with the MUSB controller. Probably to make this sharing
work, we were avoiding to declare this in the DT. This has two
shortcomings:
- U-Boot (which uses the same .dts) cannot use this port in host mode
without a PHY linked, so we were loosing one USB port there.
- It requires the MUSB driver to be enabled and loaded, although we
don't actually use it.
To avoid those issues, let's add this PHY link to the A64 .dtsi file.
After all PHY port 0 *is* connected to HCI0, so we should describe
it as this. Remove the part from the Pinebook DTS which already had
this property.
This makes it work in U-Boot, also improves compatiblity when no MUSB
driver is loaded (for instance in distribution installers).
Fixes: dc03a047df ("arm64: allwinner: a64: add EHCI0/OHCI0 nodes to A64 DTSI")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210113152630.28810-2-andre.przywara@arm.com
The AB8505 mixed signal ASIC variant has a die temperature
channel that is missing in the AB8500 variant. Add it to
the DTSI.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The setting of VMMCI differs so much between different
boards that we need to handle it on a per-board basis
rather that complicating things by overriding stuff from
the included DTSI:s. Push it down into top-level tree
instead.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the two temperature-monitoring thermistors to the
HREF reference design, defines a thermal zone for the
chassis and sets some reasonable thermal limits.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The different charger nodes in the AB8500 and AB8505
includes was missing the interrupt assignments for the
interrupts necessary to drive the AB8500/AB8505 charging
state machine.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The AB8500/AB8505 is providing ADC channels and do so
using the standard property "io-channel-names" not the
mistakenly singular form "io-channel-name".
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Cadence IP in J721E supports a maximum of 32 outbound regions. However
commit 4e5833884f ("arm64: dts: ti: k3-j721e-main: Add PCIe device
tree nodes") incorrectly added this as 16 outbound regions. Now that
"cdns,max-outbound-regions" is an optional property with default value
as 32, remove "cdns,max-outbound-regions" from endpoint DT node.
(Since this doesn't impact existing functionality, it need not be
backported to older kernels).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20210105151421.23237-2-kishon@ti.com
Per the reference manual for the RZ/G Series, 2nd Generation,
the RZ/G2M, RZ/G2N, and RZ/G2H have a bit that can be set to
choose between a crystal oscillator and an external oscillator.
Because only boards that need this should enable it, it's marked
as disabled by default for backwards compatibility with existing
boards.
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20201228202221.2327468-2-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Beacon EmbeddedWorks is introducing a new kit based on the
RZ/G2H SoC from Renesas.
The SOM supports eMMC, WiFi and Bluetooth, along with a Cat-M1
cellular radio.
The Baseboard has Ethernet, USB, HDMI, stereo audio in and out,
along with a variety of push buttons and LED's, and support for
a parallel RGB and an LVDS display. It uses the same baseboard
and SOM files as the RZ/G2M and RZ/G2N kits.
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20201224170502.2254683-8-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Beacon EmbeddedWorks is introducing a new kit based on the
RZ/G2N SoC from Renesas.
The SOM supports eMMC, WiFi and Bluetooth, along with a Cat-M1
cellular radio.
The Baseboard has Ethernet, USB, HDMI, stereo audio in and out,
along with a variety of push buttons and LED's, and support for
a parallel RGB and an LVDS display. It uses the same baseboard
and SOM as the RZ/G2M.
This SOM has only 2GB of DDR, and beacon-renesom-som.dtsi contains
the base memory node, so an additional memory node isn't necessary.
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20201224170502.2254683-7-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The SoC was expecting two clock sources with different frequencies.
One to support 44.1KHz and one to support 48KHz. With the newly added
ability to configure the programmable clock, configure both clocks.
Assign the rcar-sound clocks to reference the versaclock instead of
the fixed clock.
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20201224170502.2254683-2-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
v5.11-berlin-dts
* tag 'v5.11-berlin-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux-berlin:
ARM: dts: berlin: Use generic "ngpios" rather than "snps,nr-gpios"
ARM: dts: berlin: Fix schema warnings for pwm-leds
Link: https://lore.kernel.org/r/20201211100521.2e6f4faa@xhacker.debian
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
R40 contains deinterlace core compatible to that in H3. One peculiarity
is that RAM gate is shared with CSI1. User manual states it's separate
but that's not true. Shared gate was verified with BSP Linux code check
and with runtime tests (CPU crashed if CSI1 gate was not ungated).
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210106181901.1324075-3-jernej.skrabec@siol.net
The SL631 is a family of Allwinner V3 action cameras sold under
various names, such as SJCAM SJ4000 Air or F60 Action Camera.
Devices in this family share a common board design but can be found
with different image sensors, including the IMX179 and the OV4689.
This adds support for a common dtsi for the SL631 family as well as
a specific dts for the IMX179 fashion, which will later be populated
with an IMX179 node when a driver is available.
Features that were tested on the device include:
- UART debug
- MMC
- USB peripheral (e.g. g_ether)
- Buttons
- SPI NOR flash
Note that the exact designer/vendor of these boards is unknown.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20201206165131.1041983-6-contact@paulk.fr
This adds documentation for the compatible strings of the
SL631 Action Camera with IMX179.
Note that the device is sold under various different names, such as the
SJCAM SJ4000 Air or F60 Action Camera. This is a similar situation to
the Q8 tablets and just like them, the allwinner vendor is used as
fallback.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201206165131.1041983-5-contact@paulk.fr
This fixes a few things with the Pinecube AXP209 node:
- No compatible is required since it is using an AXP209 (not AXP203)
according to the schematics and this is what the included axp209.dtsi
already has;
- The interrupt-controller and #interrupt-cells properties are already
described in the included axp209.dtsi;
- The interrupt comes through the NMI controller, not directly through
the GIC.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20201206165131.1041983-4-contact@paulk.fr
The V3s/V3 has a NMI interrupt controller, mainly used for the AXP209.
Its address follows the system controller block, which was previously
incorrectly described as spanning over 0x1000 address bytes.
Even though this is what the Allwinner documentation indicates,
precedence from other SoCs such as the R40 suggests that this is not
actually the case.
This reduces the system controller address span up to the NMI
controller and adds a node for the controller, with its dedicated
compatible.
While the interrupt number was found in Allwinner's documentation,
the address for the controller is specified in any Allwinner SDK
supporting sun8iw8 (V3/V3s) at:
drivers/power/axp_power/axp20/axp20-board.c
It was tested to work on a V3 board with an AXP209 connected to the
NMI interrupt line.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20201206165131.1041983-3-contact@paulk.fr
The Intel eASIC N5X platform shares the same register map as the Agilex
platform, thus, we can re-use the socfpga_agilex.dtsi as the base
DTSI.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This is to remove similar errors as below:
OF: /.../gpio-port@0: could not find phandle
Commit 7569486d79 ("gpio: dwapb: Add ngpios DT-property support")
explained the reason of above errors well and added the generic
"ngpios" property, let's use it.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
