Commit Graph

1080102 Commits

Author SHA1 Message Date
Ziyuan Xu
02fc73a44b i2c: rk3x: get_version after mcu is done for thunder-boot
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: Ic3e679207ebdec79b536abd029d410ddb15a19e8
2023-06-21 19:29:02 +08:00
Su Yuefu
d4b1e00722 media: i2c: add sc223a driver
Signed-off-by: Su Yuefu <yuefu.su@rock-chips.com>
Change-Id: Id21af19d557e61b8d8e3261d7777a4d140c8d4cd
2023-06-21 16:48:09 +08:00
Ziyuan Xu
6bcac58699 media: rockchip: isp: wait RISC-V with 400ms timeout
Fixes: d0edc7b3e7 ("media: rockchip: isp: thunder boot with multi sensor")
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: If7623fd081796904b891ed7fae7cf402b52cd860
2023-06-21 16:44:01 +08:00
Damon Ding
0065c0b8f9 drm/panel: simple: add support for panels initialized by spi
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
change-Id: I4582cc98619f7b7327af68c266ba0de1163a1b63
2023-06-21 16:36:11 +08:00
Yu Qiaowei
2b39b0acb4 video: rockchip: rga3: modify over-constraint on fbcd
Change-Id: I9aa492263f036cedddc5e85485bb250770d2aafa
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
2023-06-21 14:59:20 +08:00
Jon Lin
679557456b PCIe: dw: rockchip: Delaying the link training after hot reset
Delaying the link training after hot reset, so that it's possible
to read/write some register status through the DBI.

The controller support delaying the Link Training by setting
app_dly2_en/done register.

Change-Id: Ieb34676ecd13d8b4c47b5adc34350294ddc60ace
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2023-06-21 14:42:36 +08:00
Damon Ding
528c67179b arm64: dts: rockchip: rk3562-evb: add rgb display board
Panel k350c4516t supports to be initialized by spi in
rgb mode.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Id6addc5db469acaf9a55b1d9d1b867c364526290
2023-06-20 20:45:15 +08:00
Zefa Chen
9c2112878e media: rockchip: vicap fixed error state of group mode and add some debug log
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I6484ea72caa89bd420c68d607e3fec21e2bceac1
2023-06-20 20:43:44 +08:00
Lan Honglin
cfe0bad194 ARM: dts: rockchip: update rv1106g-evb2-v10-dual-camera.dts
Support sc31iot and sc230ai
Update isp thunderboot buffer size

Change-Id: If701735b748b1329f3d90e2986ff0d6870aede65
Signed-off-by: Lan Honglin <helin.lan@rock-chips.com>
2023-06-20 20:42:33 +08:00
Elaine Zhang
423f806d76 arm64: dts: rockchip: rk3562: Add trim configure for tsadc
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I078a15cb3a8290f5233a7c04edb85870bed863f7
2023-06-20 20:38:39 +08:00
Elaine Zhang
d1b2c15f5f thermal: rockchip: Add trim temperature for rk3562
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I49a527fe1f36854ae3859636a9acfcfb36d23a50
2023-06-20 20:38:39 +08:00
Finley Xiao
7da0c1498f thermal: rockchip: Add default value for trim base
The trim_base nvmem cell is abandoned on some platforms, and use the
default value 30.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: If2ebb13de33b0928854a406cbefdcdc95cfa0947
2023-06-20 20:38:39 +08:00
Luo Wei
1a2e751d9f misc: lt7911d-fb-notifier: add firmware upgrade support
Signed-off-by: Luo Wei <lw@rock-chips.com>
Change-Id: I4deb3a0b61d4fa0605da637cf41423995ce4be0e
2023-06-20 20:36:15 +08:00
Lan Honglin
cae91899b6 ARM: configs: rockchip: rv1106 enable sc301iot for battery-ipc
Signed-off-by: Lan Honglin <helin.lan@rock-chips.com>
Change-Id: Ib844385bfd58f73eaa5f4e415d598d1f983fa4cd
2023-06-20 17:04:47 +08:00
Weiwen Chen
11e0aed493 ARM: configs: rockchip: rv1106: add recovery config
Signed-off-by: Weiwen Chen <cww@rock-chips.com>
Change-Id: I283c6b7d0e3b9fc22160ecdec237fb5a728d1c30
2023-06-20 14:59:13 +08:00
LongChang Ma
2f601384d9 meida: i2c: fix gc2503 dual sensor sync issue
Signed-off-by: LongChang Ma <chad.ma@rock-chips.com>
Change-Id: I6a7fbd29000262f676c91e470e52cf52dc3c0bd5
2023-06-20 10:24:16 +08:00
Cai YiWei
599ad4d224 media: rockchip: isp: fix uyvy format for isp32
Change-Id: I0dc34f154e989ef88ae5b5402339f60b43fbb4a0
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
2023-06-19 17:55:20 +08:00
Guochun Huang
fd58b01c8e drm/rockchip: dsi: fix RK3562_SYS_GRF_VO_CON1 offset addr
Change-Id: Ie3e3675706996ddcc2f08f7d8d743ca3f46a4f23
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
2023-06-19 08:00:20 +00:00
Lan Honglin
c3bcd08fcf media: i2c: fix sc301iot reset when probe for fastboot
[ISSUE]
device I2C communication is fail due to reset

Change-Id: I847523a8df22727b6863a4dbe2cdad11b104435c
Signed-off-by: Lan Honglin <helin.lan@rock-chips.com>
2023-06-19 10:42:46 +08:00
Zou Dengming
0d1ab9be85 arm64: dts: rockchip: rk356x boards: prepare bt sco settings
we don't directly enable all evb board to support bt-sco cards
because it may take some i2s/pcm, which may use dma,
but dmas may limit.

so we just prepare this settings, then if any one who want to
support bt-sco, he/she can just add dts in board-level dts.

now, we just enable rk3568-evb1 and rk3566-evb1 just for example.
Diff in "rk3568-evb1-ddr4-v10.dts" is like this:

+&bt_sco {
+	status = "okay";
+};
+
+&bt_sound {
+	status = "okay";
+};
+
+&i2s3_2ch {
+	status = "okay";
+};

The default pcm/i2s setting is:
Format: PCM, dsp_a, MSB first, short sync, rising edge and delay 1 bclk.
rockchip soc: master; Bt controller: slave

Change-Id: I6668bfbb87e4b0ea71a661bbcf8248cbde77974e
Signed-off-by: Zou Dengming <marsow.zou@rock-chips.com>
2023-06-19 10:41:30 +08:00
Huibin Hong
fd726f9546 arm64: dts: rockchip: rk3588-android: support minidump
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: I77c0c8623ae0f4cc702cae0633de5fc711ccb08e
2023-06-19 10:22:13 +08:00
Huibin Hong
4b10d97983 arm64: smp: minidump save cpu context when ipi stop
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: I0d98a017311aa85a509649de221873935bb16232
2023-06-19 10:21:11 +08:00
Huibin Hong
08e5018b7c fs: pstore: register buffers to minidump
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: I0c6feb839fe6a4d25bc0174659cba528ffef4975
2023-06-19 10:16:49 +08:00
Huibin Hong
d6d4beaca8 soc: rockchip: add rk minidump support
After panic or wdt reset, you can get /proc/rk_md/minidump
as minidump.elf, and debug it with gdb

Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: I6d92d9ee21e304bf72231a3f62ecab66b6ab1a43
2023-06-19 10:16:49 +08:00
Huibin Hong
28663c950f arm64: rockchip_defconfig: enable minidump
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: Iee4cca154d8e103071c28f459b2364dfd00f5544
2023-06-19 10:16:49 +08:00
Zou Dengming
3d4d03ca90 arm64: dts: rockchip: rk3588/rk3588s boards: prepare bt sco settings
we don't directly add all evb board to enable bt-sco cards
because it may take some i2s/pcm, which may use dma,
but dmas may limit.

so we just prepare this settings, then if any one who want to
support bt-sco, he/she can just add dts in board-level dts.

now, we enable rk3588-evb1 sco just for example.
Diff in "rk3588-evb1-lp4-v10.dts" is like this:

+&bt_sco {
+	status = "okay";
+};
+
+&bt_sound {
+	status = "okay";
+};
+
+&i2s2_2ch {
+	status = "okay";
+};

The default pcm/i2s setting is:
Format: PCM, dsp_a, MSB first, short sync, rising edge and delay 1 bclk.
rockchip soc: master; Bt controller: slave

Change-Id: Id161dd43ec3ea657e758852f7214727488633977
Signed-off-by: Zou Dengming <marsow.zou@rock-chips.com>
2023-06-19 09:44:02 +08:00
Finley Xiao
643ea50b93 clk: rockchip: Implement rockchip_clk_register_armclk_v2()
The clock path of CPU may be simplified as follows:

  --gpll--|--\
          |   \
          |    \
          |     \
 --v0pll--| mux |--[gate]--[div]--clk_core--
          |     /
          |    /
 --v1pll--|   /
          |--/

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ia8b56830a77130e12454dcff9a5de83a5c868fd9
2023-06-16 18:19:51 +08:00
Bian Jin chen
3868949da6 mali400: Fix compilation errors on clang-r487747c.
Signed-off-by: Bian Jin chen <kenjc.bian@rock-chips.com>
Change-Id: I2c4bbf5fb7513eca3cc7f01963dd977b7fd58462
2023-06-16 18:07:41 +08:00
Bian Jin chen
188560e5f3 net: wireless: rockchip_wlan: bcmdhd: Fix compilation errors on clang-r487747c.
Signed-off-by: Bian Jin chen <kenjc.bian@rock-chips.com>
Change-Id: Iab5692494dd926d3b186d5d0b75a74b1624bd874
2023-06-16 18:07:19 +08:00
Jon Lin
a25a517ce4 spi: rockchip: Modify the slave tx finish judgement
The SR register of the old version IP SPI slave tx transmission
process will remain in a busy state, so it needs to be processed
by determining the tx empty status bits filed.

Change-Id: If71ed842e2b7aed3cfe22d7bc401ea2d0bb1409b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2023-06-16 10:05:12 +08:00
Damon Ding
68382fc3ee drm/rockchip: vop: add check if global/pixel alpha both enable
VOP in RK3308 supports global alpha and pixel alpha.
Only one alpha mode can be enabled at the same time.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ia749deeb82a31b7e5298ca14586bbfb75606469f
2023-06-16 09:58:34 +08:00
Damon Ding
21815401b7 drm/rockchip: debugfs: add support to enable color bar
Enable horizontal color bar:
    echo 1 > /sys/kernel/debug/dri/0/video_port0/color_bar
Enable vertical color bar:
    echo 2 > /sys/kernel/debug/dri/0/video_port0/color_bar
Disable color bar:
    echo 0 > /sys/kernel/debug/dri/0/video_port0/color_bar

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I63ed8f2a3a2fafc852151fda03b91b926a8e4470
2023-06-16 09:57:05 +08:00
Xing Zheng
4700405386 ASoC: rockchip: rk817-codec: remove some useless SOC_ENUM_SINGLE_DECLs
Change-Id: Ibc351c03518152ac463f54aa1fa8640083352aa8
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2023-06-16 09:51:41 +08:00
Elaine Zhang
eebe228530 clk: rockchip: rk3568: fix pwm clk register description
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I30a8c97c95be15ea23a485e9e429fd575605b38a
2023-06-16 09:49:51 +08:00
Xing Zheng
ed36cde37c ASoC: rockchip: rk817-codec: Fix a large number of mclk counts being enabled
If it is not controlled, when the path is configured after
resume, the clock will be continuously turn on to increase
the clock count.

Therefore, we can count and control the switch of clock
separately according to the current status of playback and
capture, so as to avoid that mclk is accidentally turned off
when playback and capture exist at the same time, causing
the other stream to fail to work.

For example:
- before:
  mclk_sai0          2        2        0    11289600          0     0  50000
     mclk_sai0_out2io       1        1        0    11289600          0     0  50000
        mclk_sai0_to_io      16       16        0    11289600          0     0  50000

- after:
  mclk_sai0          2        2        0    11289600          0     0  50000
     mclk_sai0_out2io       1        1        0    11289600          0     0  50000
        mclk_sai0_to_io       2        2        0    11289600          0     0  50000

Change-Id: I78ec18c7ffc42f548e82357bcf20701aa057f15d
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2023-06-16 09:39:22 +08:00
Xing Zheng
b2f8e21628 ASoC: rockchip: rk817-codec: re-support recover playback/capture path after resume
We can configure automatically playback/capture path via
the controlling of 'Resume Path'.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: Ie00e7a673bff068aa922e322d833106f4cbacfde
2023-06-16 09:39:22 +08:00
Jon Lin
d8d884fca6 spi: rockchip-test: Check the spi sync actual length
Change-Id: I4a189c50cc9aa9c6151e9efcfa5eca59eb35f44a
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2023-06-16 09:30:52 +08:00
Jon Lin
0f7fb69548 spi: rockchip: Add transfer completion wait
Add transfer completion wait to improve software compatibility,
1.Support to adjust he timeount value if needed
2.Return the fail result when spi slave abort

Choose to discard the rx fifo data after slave abort instead of
attempting to modify xfer->len to change the framework layer
mechanism.

Change-Id: I6bb1ba0ba12ad7486117aff5e948616c8e768418
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2023-06-16 09:30:52 +08:00
Jon Lin
a1ab78c641 mtd: spinand: xincun: Add code
XCSP2AAPK

Change-Id: I205dbef7f1f3b24c4897bfe0ffd4c0b67ce04396
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2023-06-16 09:10:17 +08:00
Xing Zheng
0c8ca14156 ASoC: rockchip: sai: keeping naming style of 'rockchip_' prefix for sai_suspend/resume
Change-Id: I33a4d88acf8f12ea0f1440cf8ce4bd2a57ea466e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2023-06-14 21:15:48 +08:00
Xing Zheng
f002e5acff ASoC: rockchip: sai: Add support system PM suspend/resume
Change-Id: Iafce14494982a3827f0a43409cfffe53307b7193
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2023-06-14 21:15:48 +08:00
Luo Wei
bccf896daf arm64: dts: rockchip: add rk3588 vehicle evb v21 dts for demo
Signed-off-by: Luo Wei <lw@rock-chips.com>
Change-Id: I9cdd03881fa8ee954f6fcdcfb17b3129677180bd
2023-06-14 19:44:00 +08:00
Sandy Huang
77c6054e48 drm/rockchip: vop: fix alpha mode error for vop lite
1. vop lite can't support pixel-alpha + scale and can support global
alpha + scale;
2. global alpha must be non-premul alpha mode;
3. vop lite and vop full premul alpha config bit is reversed;
4. vop full add premul and non-premul config from userspace;

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ic42892eac39f07a41d46ed1a77398862f37894c0
2023-06-14 19:39:38 +08:00
Sandy Huang
15a4dfb123 drm/rockchip: vop2: fix esmart pd always be closed and lead to show black screen
without this commit, esmart pd will always be closed when uboot not use
esmart1/2/3 to show logo(enable smart pd), and lead to esmart1/2/3 layer
show black screen.

Fixes: c4a31b3e3a ("drm/rockchip: vop2: power on esmart pd without ref count")
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I20474745a31a813b97223345a4582a3e9da80cfe
2023-06-14 19:36:55 +08:00
Tao Huang
d322685333 mm/readahead: Fix for GKI
Fixes: c73d891d8e ("mm: optimize readahead for the file with fscrypt")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I1db7d429e5ce34330d5c2d6737b520d3b6779977
2023-06-14 16:17:22 +08:00
Zhen Chen
73b5dde370 MALI: bifrost: Not to call kbase_ipa_reset_data() if rockchip simple-power-model is used
When rockchip simple-power-model is used,
kbase_ipa_reset_data() for the default mali power models should not be called.

The issue is exposed by the following exception logs:
[    3.406039] ------------[ cut here ]------------
[    3.406056] DEBUG_LOCKS_WARN_ON(lock->magic != lock)
[    3.406081] WARNING: CPU: 1 PID: 154 at kernel/locking/mutex.c:955 __mutex_lock_common+0x974/0xbc0
[    3.406094] Modules linked in:
[    3.406111] CPU: 1 PID: 154 Comm: kworker/u16:3 Not tainted 5.10.157 #110
[    3.406118] Hardware name: Rockchip RK3588 EVB1 LP4 V10 Board (DT)
[    3.406132] Workqueue: devfreq_wq devfreq_monitor
[    3.406144] pstate: 60c00009 (nZCv daif +PAN +UAO -TCO BTYPE=--)
[    3.406152] pc : __mutex_lock_common+0x974/0xbc0
[    3.406161] lr : __mutex_lock_common+0x974/0xbc0
...
[    3.406342] Call trace:
[    3.406351] __mutex_lock_common+0x974/0xbc0
[    3.406361] mutex_lock_nested+0x50/0x5c
[    3.406374] kbase_ipa_reset_data+0x40/0x154
[    3.406384] kbase_devfreq_status+0x60/0x90
[    3.406394] devfreq_simple_ondemand_func+0x34/0x104
[    3.406401] update_devfreq+0x60/0xf0
[    3.406408] devfreq_monitor+0x34/0x9c
[    3.406421] process_one_work+0x218/0x358
[    3.406429] worker_thread+0x230/0x4e0
[    3.406439] kthread+0x144/0x160
[    3.406449] ret_from_fork+0x10/0x30

Fixes: 68c4487930 ("MALI: bifrost: not to call kbase_ipa_init() if rockchip simple-power-model is used")
Change-Id: I5fb5d4b6e63df77e6ea45ab3c60d627e3d0a03a2
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
2023-06-14 15:05:49 +08:00
Caesar Wang
f0a0c64287 arm64: dts: rockchip: add camera dtsi on rk3562-evb2-ddr4-v10-linux.dts
Including rk3562-evb2-cam.dtsi for dual camera configuration in
rk3562-evb2-ddr4-v10-linux.dts

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: If454c0561efd7936a266b9a224bf35f3dc68ba38
2023-06-14 14:34:49 +08:00
Caesar Wang
7836b77050 arm64: dts: rockchip: Assign VOP_ACLK to 750MHZ for rk3588-linux.dtsi
On the RK3588 platform, 8K display is an important feature, but it also
increases system power consumption if the product is concerned about
power consumption, 8K can be turned off by default.

Currently, support for 8K display is enabled by default on Linux
platforms, requiring an increase in the aclk of vop to 750MHZ.

Tested on RK3588 EVB, as below:

root@linaro-alip:/# cat /sys/kernel/debug/clk/clk_summary |grep aclk_vop
aclk_vop    1        4        0   750000000          0     0  50000

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I6f4dd01140fe8fc9115ebc4cf8100f84f1592bbf
2023-06-14 11:41:00 +08:00
Damon Ding
6fe07fe661 pwm: rockchip: enable dclk scale function in oneshot mode
This is a workaround, an uncertain waveform will be
generated after oneshot ends. It is needed to enable
the dclk scale function to resolve it. It doesn't
matter what the scale factor is, just make sure the
scale function is turned on, for which we set scale
factor to 2.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: If34837194cba89570a58a993d7133a852955f69c
2023-06-13 16:22:57 +08:00
Tao Huang
8c43b7ff27 soc: rockchip_system_monitor: Fix TPYE -> TYPE typo
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I815c6e01039c0ba6469b575cf86349e6b87148c5
2023-06-13 15:28:39 +08:00