At VOP3_ESMART_2K_2K_2K_2K_MODE mode, esmart can support:
4k scale down to 2k or 2k scale up to 4k, but can't support 4k to 4k,
current property[INPUT_WIDTH/INPUT_HEIGHT/OUTPUT_WIDTH/OUTPUT_HEIGHT]
can't accurately describe this feature, so we agreement on rules with hwc:
1. when esmart can support 2k->4k/4k->2k, can't support 4k->4k, the property
value is:
INPUT_WIDTH:4096
OUTPUT_WIDTH:2048
2. when esmart can suport 2k->4k/4k->2k/4k->4k, the property value is:
INPUT_WIDTH:4096
OUTPUT_WIDTH:4096
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: If2067f34a36ba77249174e8369eaaccb0a8f700f
vop2->esmart_lb_mode is correct value according driver default value and
dts config.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I1c242ebbb47cdf2916a56ae729ba65222d31d0d5
If not to enable uboot logo, neither to set plane
mask in dts. For RK3568 and RK3588, it is needed to
assign plane mask by default.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I9ebbc32b89b503784a225cc482e7cbde15508843
Bar2 mapped memory resource do not have outbound configured and
can be used as general memory, using write buffer to improve data
transform rate.
Change-Id: I0b1e86ec47432e1cd13ee10db4895eca071db45d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
For small capacity RAM, the value of this address is too large
Change-Id: Iccc318e5d97ec1df2e8cfc7a651022b1a33e1010
Signed-off-by: Jianlong Wang <jianlong.wang@rock-chips.com>
The esmart pd attach to esmart1/esmart2/esmart3, if we want to
turn off esmart pd, a vp attach to esmart1, esmart2 or esmart3
must active.
Now, the esmart pd is turn off when the last vp is disable, if
the last vp is not attach to esmart1, esmart2 or esmart3, the
esmart pd will turn off failed.
To fix this issue, when disable the last vp, we will active the
vp attach emsart1 and turn off the esmart pd.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ide8a367de2c8b7ba027568bc7eacb3fd389c73fe
Add capability to parse and retrieve max DP link supported rate
from link-frequencies property of output endpoint.
Change-Id: I7fdc0f509eef3043d3940fe2639b3fbbc61fbfec
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Add capability to parse and retrieve max DP link supported rate from
link-frequencies property of output endpoint.
Change-Id: Ie3fbf7baa88503a04309ace6ecf004b23fb0bb78
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Pass '-B 0x200' to mkimage to align the FIT structure and data to 512 byte.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I56286064e8db62e4ae236e15a3de6827a577f506
Enable the following macros for AMP system:
CONFIG_ROCKCHIP_AMP=y
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: Ic8eafe34df524f3713a6894ff1b18dc10b124896
Fix V7:
undefined reference to `__stack_chk_guard'
Change-Id: Ie7b7cf74d16fb058acbad63c86c9ad8d9543032e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
All GMSL2 devices have multi-function pins (MFP)
that can be used as general-purpose input and output (GPIO)
pins or for other functionality (e.g., I2C, I2S, SPI, etc.).
Change-Id: Idba149389c134d55a1c51c90fc889f859c064e4c
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
All GMSL2 devices have multi-function pins (MFP)
that can be used as general-purpose input and output (GPIO) pins
or for other functionality (e.g., I2C, I2S, SPI, etc.).
Change-Id: I385593e85a0e52cc1500fd74075d524d178784ce
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
1/ update Copyright
2/ The backlight is for the eDP panel and it has the connector on the
excavator baseboard.
3/ remove cdn_dp
Fixes: 5a2a93f1ee ("arm64: dts: rockchip: move backlight from rk3399 sapphire to excavator")
Change-Id: I513fb62c8f8869a5a6151777c86da3dace362ede
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
When set framerate from small one to big one, will lead to discard
all frame because the is_diacard flag is not reset to "false" in the
change.
Signed-off-by: LongChang Ma <chad.ma@rock-chips.com>
Change-Id: I7197d40ec0053c7dad7f2c088d77f7493626ea90
CA info should be ignored in the ELD Bypass Situation.
Fixes: c6c61f8679 ("ASoC: hdmi-codec: Add option for ELD bypass")
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I02265570ebcf4d17558b604644dcf5e9425f06cb
Test on RK3588S Tablet, set the power supply of logic on
and set the power supply of usb2 phy off during deep sleep,
then the id falling edge interrupt will be triggered after
system resume, and kernel panic with the following log:
SError Interrupt on CPU0, code 0xbe000011 -- SError
CPU: 0 PID: 1946 Comm: kworker/0:0 Not tainted 5.10.110 #600
Hardware name: Rockchip RK3588S TABLET RK806 SINGLE Board (DT)
Workqueue: events rockchip_usb2phy_otg_sm_work
pstate: 20c00009 (nzCv daif +PAN +UAO -TCO BTYPE=--)
pc : _raw_spin_unlock_irqrestore+0x28/0x60
lr : regmap_unlock_spinlock+0x18/0x28
......
Kernel panic - not syncing: Asynchronous SError Interrupt
CPU: 0 PID: 1946 Comm: kworker/0:0 Not tainted 5.10.110 #600
Hardware name: Rockchip RK3588S TABLET RK806 SINGLE Board (DT)
Workqueue: events rockchip_usb2phy_otg_sm_work
Call trace:
dump_backtrace+0x0/0x1c8
show_stack+0x1c/0x2c
dump_stack_lvl+0xdc/0x12c
dump_stack+0x1c/0x64
panic+0x150/0x3a4
test_taint+0x0/0x30
arm64_serror_panic+0x78/0x84
do_serror+0xe0/0x100
el1_error+0x94/0x118
_raw_spin_unlock_irqrestore+0x28/0x60
regmap_unlock_spinlock+0x18/0x28
regmap_write+0x68/0x84
rockchip_usb2phy_power_on+0x128/0x1f0
rockchip_usb2phy_otg_sm_work+0x1d0/0x454
process_one_work+0x1f4/0x490
worker_thread+0x278/0x4dc
kthread+0x13c/0x344
ret_from_fork+0x10/0x30
In fact, there are two issues here.
1. The power of phy id belongs to the usb2 phy power supply.
And the id is pulled up to high level by default. So if we
power off usb2 phy supply during deep sleep, the id status
will fall to low level and trigger the falling edge interrupt.
In the id irq handler rockchip_usb2phy_id_irq(), it send Host
notification only depends the id falling edge irq status, it's
not enough in this case, it needs to check the iddig status
to make sure that the id status is indeed in low level.
2. For RK3588S, the pipe phystatus select register from the
usb grf, and the power domain of usb grf belongs to PD_USB.
So we must make sure the PD_USB is on when operate the pipe
phystatus select register. Originally, we operated the pipe
phystatus register in the phy ops of power_on, because we
expected that the phy ops of power_on called from the dwc3
controller pm runtime resume process which can power on the
PD_USB. However, in this test case, if the id falling edge
interrupt after system resume, the phy ops of power_on can
be called when PD_USB is off.
The call stack:
rockchip_usb2phy_id_irq()
-> send Host notification ->
rockchip_otg_event()
-> receive notification and schedule otg_sm_work ->
rockchip_usb2phy_otg_sm_work()
-> detect EXTCON_USB_HOST is set and call phy power_on ops
rockchip_usb2phy_power_on()
-> set the pipe phystatus select register
Change-Id: Ib7e5bc095ab1df2ca4c983d58a9f15720f0cccb9
Signed-off-by: William Wu <william.wu@rock-chips.com>
The configuration of flip/mirror would take effect in the half of frame,
which cause frame corruption. To make sure the flip/mirror configuration
is took effect in the next frame, we should enable register frame buffer
on gc4653.
Signed-off-by: Zhichao Yu <zhichao.yu@rock-chips.com>
Change-Id: Ibf85eb46d7c22785a820bcf781bd3e96a3455f00
