1. config vp1 pre_dither_down at split mode;
2. disable pre_dither_down at YUV 10/8 bit output and RGB 10 bit output;
3. enable pre_dither_down at RGB 8/6 bit output;
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I304fc66324c97e3e4f50e03b8c8c2c1835871b1a
1. NV12/NV16/YUYV xoffset must aligned as 2 pixel;
2. NV12/NV15 yoffset must aligned as 2 pixel;
3. NV30 xoffset must aligned as 4 pixel;
4. NV15/NV20 xoffset must aligend as 8 pixel at rk3568/rk3588/rk3528/rk3562,
others must aligned as 4 pixel;
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I28d69d1f8189963170ef798c12bfd60fb092ef20
The legacy api drmModeCrtcSetGammalegacy can be called independently, so it need extra config done;
and the atomic api have config done at the vop2_crtc_atomic_flush();
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Idca4c42f1d298ec312dc839ee526e4132d9d8b73
At interlace mode, the adjusted_mode->crtc_vdisplay will be div2 from vdisplay,
but the userspace is still set as adjusted_mode->vdisplay.
Fixes: bfc49df515 ("drm/rockchip: vop3: plane display size check use crtc_* parameter is more correct")
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I6765e5486dc4d15b0b34b75370280d48500ef4da
fixes error of:
rockchip-csi2-dphy csi2-dcphy0: Only CSI2 type is currently supported
rockchip-csi2-dphy csi2-dcphy0: driver could not parse port@1/endpoint@0 (-22)
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: Ie559585300f30acc227df578fc41fefc5278f0ee
Fixes: 13639746fa ("phy: rockchip: naneng-combphy: Fix swing to 650mv under 100M refclk for rk3562")
Change-Id: If9bf594ec4183d4be62dd1f9edb24ecd30915f78
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Fix 2 issue:
1.The array_index_nospec will clamp the index within the range of
[0, size).If no core is idle, it still return core_id = 0 that will
cause core 0 dispatch to work.
2.Disable a core dose not take effect.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I939b0eee16fcec495b8cfe87aff3cb3e59044e5e
The FBS feature may not be re-enabled if an error occurred
during soft reset. If the host supports FBS, this patch will
re-enable FBS at the end of soft reset.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I821bf5362c6be8ddf142823ad6b6268c797bcded
1/ disable CONFIG_DM_VERITY
On Linux OS, it is not necessary to enable CONFIG_DM_VERITY by default,
only required if secureboot or security related functions are enabled.
2/ adjusting the config order
make ARCH=arm menuconfig, then make ARCH=arm savedefconfig
to check.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: If0c11c32bf3ea42a36fa7fa12fbd9cc4a464e200
register PDM_SYSCONFIG is marked as volatile, and for regcache
sync policy, it will skip the registers which marked as volatile.
so, we should do it after regcache sync.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ic65bc28d14fefc6e6c70e1b2c26468aa0fcd142e
from commit: 5b7261b mtd: spinand: winbond: Add support for Winbond W35N01JW SPI NAND flash
Change-Id: Iabca09af99d7b94150c847653faf0275228b7144
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
from commit: 5b7261b mtd: spinand: winbond: Add support for Winbond W35N01JW SPI NAND flash
Change-Id: Iabca09af99d7b94150c847653faf0275228b7144
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
On the QUIRKS_ALWAYS_ON path, we bring up the clk path on probe
to achieve the clk always on function.
for this situation, the refcount always true, so, we should save
the stream dma state on pause and then do restore on resume.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I8e45b78a475a468880ef2fb0b358dbdd1169ff08
CLK_ALWAYS_ON should be placed after all registers write done,
because this situation will enable XFER bit which will make
some registers(depend on XFER) write failed.
Fixes: 3644caf8de ("ASoC: rockchip: i2s-tdm: Add support for clk always-on")
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iffcfed18d3805ee575df4e8cf267d4ef6a3fa866
Fixes: 13639746fa ("phy: rockchip: naneng-combphy: Fix swing to 650mv under 100M refclk for rk3562")
Change-Id: If9bf594ec4183d4be62dd1f9edb24ecd30915f78
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Fixes: c3f038c2dc ("PCI: rockchip: dw_ep: Delaying the link training after hot reset")
Change-Id: I9e14995caecce709d93d33b9e2b568a5eae91273
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Assign VOP_ACLK to 750MHZ at rk3588s.dtsi, so reverts this commit 7836b77050.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I1dd48012246eb4d52d748bf489128fcf2885c30f
Assigned RK3588 VOP_ACLK as 750MHZ by default to support 8k output and improve
VOP performance.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ia4c75a9f04c655e4b26867bc87023812cdc7f82f
The I2S-TDM on Rockchip SoCs only support one data lane for tx and one
data lane for rx, but the codec devices may requires a normal tdm work
with more than one data lane.
Enable the TDM_MULTI_LANES to allow driver works under a higher sample
rate and with more data lanes.
More detail, see the driver patch comment.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Idbeeb00d4903e49fb3c0c3dfbb16b55125fe2da7
The former method makes ECC effective value decreased from 4 to 1.
Change-Id: I069e62432bb339356070f5228fc7d65daca7b696
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
The former method makes ECC effective value decreased from 4 to 1.
Change-Id: Ie5f37e291166661def40db015eac63c003719785
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
pinctrl-default/idle/clk must be paired in the same iomux group.
DON'T USE pdm1m0-default with pdm1m1-idle
Ref: commit: 0d9748600792 ("ASoC: rockchip: pdm: Fix clk glitch on runtime PM")
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iea86fc5a16eaec8b39c31708228732b49ccda5d7
For controller which is managed by PD (power-domain),
when PD off, the controller is reset to the default
status, and the FRAC-DIV is a fixed value(1/20).
Once the mclk is enabled, there are some high freq cycle
leak, to fix this issue, we use the pinctrl-idle to
block these cycles until the config has been come back
to the normal state.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I4e34129277cffa7bc443b6addfb1e26b70bf546e
