the driver has a bug in calc of page num when virtual
address may not 4k align
Change-Id: I65e8d3017a0365409a69e2edce12f2d302bca298
Signed-off-by: Shixiang Zheng <shixiang.zheng@rock-chips.com>
The spi5 request number is at DMAC0, others are at DMAC1.
Change-Id: I16ce63617d841f867eb7c831a05145b808f2a1d3
Signed-off-by: David Wu <david.wu@rock-chips.com>
On Freescale i.MX7D platform, all clocks operations, including
enable/disable, rate change and re-parent, requires its parent clock on.
Current clock core can not support it well.
This patch adding flag CLK_OPS_PARENT_ENABLE to handle this special case in
clock core that enable its parent clock firstly for each operation and
disable it later after operation complete.
The patch part 2 fixes set clock rate and set parent while its parent
is off. The most special case is for set_parent() operation which requires
all parents including both old and new one to be enabled at the same time
during the operation.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
[sboyd@codeaurora.org: Move set_rate tracepoint after prepare_enable]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit fc8726a2c0)
Change-Id: I8b71c9081a70b13f29a2c12a5b9eae5468c26ec4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
On Freescale i.MX7D platform, all clocks operations, including
enable/disable, rate change and re-parent, requires its parent
clock enable. Current clock core can not support it well.
This patch introduce a new flag CLK_OPS_PARENT_ENABLE to handle this
special case in clock core that enable its parent clock firstly for
each operation and disable it later after operation complete.
The patch part 1 fixes the possible disabling clocks while its parent
is off during kernel booting phase in clk_disable_unused_subtree().
Before the completion of kernel booting, clock tree is still not built
completely, there may be a case that the child clock is on but its
parent is off which could be caused by either HW initial reset state
or bootloader initialization.
Taking bootloader as an example, we may enable all clocks in HW by default.
And during kernel booting time, the parent clock could be disabled in its
driver probe due to calling clk_prepare_enable and clk_disable_unprepare.
Because it's child clock is only enabled in HW while its SW usecount
in clock tree is still 0, so clk_disable of parent clock will gate
the parent clock in both HW and SW usecount ultimately. Then there will
be a child clock is still on in HW but its parent is already off.
Later in clk_disable_unused(), this clock disable accessing while its
parent off will cause system hang due to the limitation of HW which
must require its parent on.
This patch simply enables the parent clock first before disabling
if flag CLK_OPS_PARENT_ENABLE is set in clk_disable_unused_subtree().
This is a simple solution and only affects booting time.
After kernel booting up the clock tree is already created, there will
be no case that child is off but its parent is off.
So no need do this checking for normal clk_disable() later.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit a4b3518d14)
Change-Id: Idad6e0b3c7e5be87150698257f3fea15061a207e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This can be useful when clock core wants to enable/disable clocks.
Then we don't have to convert the struct clk_core to struct clk to call
clk_enable/clk_disable which is a bit un-align with exist using.
And after introduce clk_core_{enable|disable}_lock, we can refine
clk_enable and clk_disable a bit.
As well as clk_core_{enable|disable}_lock, we also added
clk_core_{prepare|unprepare}_lock and clk_core_prepare_enable/
clk_core_unprepare_disable for clock core to easily use.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit a6adc30ba7)
Change-Id: Ie4e31b0d6d638f74ee2304735ddec0eecb56d70e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
No function level change, just moving code place.
clk_disable_unused function will need to call clk_core_prepare_enable/
clk_core_disable_unprepare when adding CLK_OPS_PARENT_ENABLE features.
So move it after clk_core_disable_unprepare to avoid adding forward
declared functions later.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit 7ec986efed)
Change-Id: I3f67a5949ef1d2f5091be318d9dacbefa0495af3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
gpio4c2 default status is pull up, when it connect to bt module,
that cause this pin default voltage level to 0.8V, it may trigger
irq. So set this pin default status to pull none.
Change-Id: I48f0e22198f200b05c71b4330602e8f638cf997a
Signed-off-by: Lin Huang <hl@rock-chips.com>
user_atom.atom_number can be indirectly controlled by user-space,
hence leading to a potential exploitation
of the Spectre variant 1 vulnerability.
This issue was detected with the help of Smatch:
drivers/gpu/arm/midgard/mali_kbase_jd.c:1397 kbase_jd_submit() warn:
potential spectre issue 'jctx->atoms' [r]
katom = &jctx->atoms[user_atom.atom_number];
Fix this by sanitizing user_atom.atom_number
before 'katom = &jctx->atoms[user_atom.atom_number];'.
Notice that given that speculation windows are large, the policy is
to kill the speculation on the first load and not worry if it can be
completed with a dependent load/store [1].
[1] https://marc.info/?l=linux-kernel&m=152449131114778&w=2
Fixes: 5cf27d0b60 ("Mali: midgard: changes to enlarge BASE_JD_ATOM_COUNT to 512, for defect 184210")
Change-Id: If52f30d29a80a06c6693ddadd5947ab9fe8fbc25
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
Change the order in which the sound card is used. The rk809 sound card is
used by default for card0.
This will keep the status on original, and just add the hdmi sound card
for rk3399pro evb board.
Says the cards order as below.
[root@rk3399pro:/]# cat /proc/asound/cards
0 [rockchiprk809co]: rockchip_rk809- - rockchip,rk809-codec
rockchip,rk809-codec
1 [rockchiphdmi ]: rockchip_hdmi - rockchip,hdmi
rockchip,hdmi
Fixes: 313c342e9a
("arm64: dts: rockchip: add hdmi-sound for rk3399pro evb board")
Change-Id: Ia14f5703f6b79795cd7504fa35a23a550178b82f
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This reverts commit 987105c1ff.
According to DWC2 Programmer's Guide, 2.1.1.2 Dedicated TxFIFO Operation,
more space allocated in the transmit IN Endpoint FIFO results in a better
performance on the USB and can hide latencies on the AHB.
So this patch sets the depth of TxFIFO number 1 to 1024 Bytes which is
usually used for primary USB function (e.g MTP).
Test on RK3288 EVB Android P:
Without this patch: MTP over eMMC - Read is only 9.48 MBps
With this patch: MTP over eMMC - Read is 28.4 MB/s
Side effect of this patch, if the user uses UVC function, it need to
change the depth of TxFIFO number 1 to 512 Bytes (used for UVC control
ep), and change the depth of TxFIFO number 2 to 1024 Bytes (used for
UVC stream ep). The dwc_otg_310 driver has provided module_param to
set the depth of TxFIFO for each number. You can set the depth of TxFIFO
number 1 in cmdline like this:
dwc_otg.dev_tx_fifo_size_1=0x80,dwc_otg.dev_tx_fifo_size_2=0x100
Change-Id: I7cebf112731e43f89994b92729bf2a3f9e54e8dc
Signed-off-by: William Wu <william.wu@rock-chips.com>
To avoid bring some noise dues to unstable micbias.
Change-Id: I0127505f0adeacda5d852ae3cefae2fb5f4ee9d2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
rockchip_i2s.c driver update the DSP_A & DSP_B config,
so we update the dts config.
Change-Id: Ida013540f263d082e20d65a43c3de932aca9f906
Signed-off-by: Xiaotan Luo <lxt@rock-chips.com>
DSP_A: PCM delay 1 bit mode,L data MSB after FRM LRC
DSP_B: PCM no delay mode,L data MSB during FRM LRC
Change-Id: I198519c431815de3ca1fc154da78773ca705f0e0
Signed-off-by: Xiaotan Luo <lxt@rock-chips.com>
Add cru regs dump when system panic.
It's just for debug.
Change-Id: Ic60f491d549e030490c14ea78f4857a8cead596d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add cru regs dump when system panic.
It's just for debug.
Change-Id: I7f9bc78deef60b1fa48bada5b1a6203185ddce48
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add cru regs dump when system panic.
It's just for debug.
Change-Id: Ic4efc985892cbcc5e561203fe8e00dba116439e7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add cru regs dump when system panic.
It's just for debug.
Change-Id: Ide2c3e8add083934672f6d22d8182bcfde046783
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add cru regs dump when system panic.
It's just for debug.
Change-Id: I86ff4f12ed932431d131d22a307360418e2e9f40
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
