The reported scale was only correct for the default settings of 100 ms
integration time and gain 1.
This aligns the reported scale with the behaviour of any other IIO driver
and the documented ABI, but may require userspace changes if someone uses
non-default settings.
Change-Id: I969d50d317f20d05d26db74d497dba790b5a7c25
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
(cherry picked from commit 3525d7cfb7)
Instead of manually iterating the array of allowed gain values, use
find_closest. Storing the current gain setting avoids accessing the
hardware on each query.
Change-Id: Ibd41d58d50c29fdf17609d0323d8d54bdf3109a7
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
(cherry picked from commit e794bf6751)
Instead of reading the value from the register on each query, store the
set value.
Change-Id: If7930543623f78abb67f33106c0c0a12d4e1ac33
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
(cherry picked from commit df698c0402)
This improves code uniformity (range checks for als_gain are also done
in the setter). Also unmangle rounding and calculation of register value.
The calculated integration time it_ms is required in the next patch of
the series.
Change-Id: I5a315428927056b72899e303019d64f20ee34cbf
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
(cherry picked from commit 1e2ed3d0d2)
This patch adds support for STMicro VL6180 - ALS, range and proximity sensor. Sensor is capable of measuring the light
intensity as well as object distance using TOF (Time of Flight) technology.
Change-Id: I5ad6d2c2a93d5906aebfda6cb2cff332bc7c2462
Signed-off-by: Manivannan Sadhasivam <manivannanece23@gmail.com>
Signed-off-by: Peter Meerwald-Stadler <pmeerw@pmeerw.net>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
(cherry picked from commit 5e7f47e495)
For pixel clock is rounded by 1000Hz, the recalcated clock rate
of fractional frame rate mode, such 59.94/29.97/23.97Hz, is need
to take the 1000Hz rounding. Otherwise it will not find the pre-pll
settings when powering up phy.
Change-Id: I0f02bbede9314d57d97c539cd995eb0f67295cfd
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Set the default value for pd_idle,sr_idle and standby_idle.
Change-Id: Idfa2d62229fd8ec1ab48c2506a6b5ba3da080a49
Signed-off-by: YouMin Chen <cym@rock-chips.com>
This patch add rockchip,card-name, and add rockchip,codec-hp-det
if with acodec for vad-sound.
Change-Id: Ib81651f9b52933f24257a42e977a5382da745df8
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
If we need to extend custom audio features, using multicodec
is much more convenient than limited simple-card.
Change-Id: I784e38d33ded9a7dd9c253595611f343a4dcd566
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Usually, there are 2 groups of sample rates on audio system:
a) 8000/16000/32000/48000/64000/96000/192000
b) 11025/22050/44100/88200/176400
If the platform provides two suitable multiples of the
PLLs(e.g VPLL0@1179648000, VPLL1@903168000 on RK3308),
we can switch the mclk src to VPLL0 if sample rate
belongs a) group, otherwise, switch the mclk src to
VPLL1. Also, we need to ensure that the numerator of
fractional division is equal to 1. And we need to set
a suitable reference frequency for the parent of mclk:
group a) is 192000*256=49152000Hz
group b) is 176400*256=45158400Hz
The following is the calibrated i2s_8ch_2 on RK3308 EVB:
========
// VPLL0=1179648000Hz, VPLL1=903168000Hz
// @8000Hz, root is VPLL0，mclk=2048000Hz, FRAC division, numerator is 1
ff5001f0: 00000417 00010018 00000013 00000000
// @11025Hz, root is VPLL1，mclk=2822400Hz, FRAC division, numerator is 1
ff5001f0: 00000513 00010010 00000013 00000000
// @16000Hz, root is VPLL0，mclk=4096000Hz, FRAC division, numerator is 1
ff5001f0: 00000417 0001000c 00000013 00000000
// @22050Hz, root is VPLL1，mclk=5644800Hz, FRAC division, numerator is 1
ff5001f0: 00000513 00010008 00000013 00000000
// @32000Hz, root is VPLL0, mclk=8192000Hz, FRAC division, numerator is 1
ff5001f0: 00000417 00010006 00000013 00000000
// @44100Hz, root is VPLL1, mclk=11289600Hz, Integer division direclty
ff5001f0: 0000014f 00010006 00000013 00000000
// @48000Hz, root is VPLL0, mclk=12288000Hz, Integer division direclty
ff5001f0: 0000005f 00010006 00000013 00000000
// @64000Hz, root is VPLL0, mclk=16384000Hz, Integer division direclty
ff5001f0: 00000047 00010006 00000013 00000000
// @88200Hz, root is VPLL1 mclk=22579200Hz, Integer division direclty
ff5001f0: 00000127 00010006 00000013 00000000
// @96000Hz, root is VPLL0, mclk=24576000Hz, Integer division direclty
ff5001f0: 0000002f 00010006 00000013 00000000
// @176400Hz, root is VPLL1, mclk=45158400Hz, Integer division direclty
ff5001f0: 00000113 00010006 00000013 00000000
// @192000Hz, root is VPLL0, mclk=49152000Hz, Integer division direclty
ff5001f0: 00000017 00010006 00000013 00000000
========
Change-Id: I6776f96e92790ba83a7d0f5caeeaf917dff5e5c5
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
By default the i2s-tdm supports asymmetric sample rate,
we just set mclk tx or rx during playback or capture.
Change-Id: I1a9786a64b956c68bb5ba8796d2742f5b142b124
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
We need to using stream to know whether is playback
or capture in sys_clk.
Change-Id: If392c0bc6a6b7d9309ca8ee5b33945d42193792e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This patch supports headphone jack for rockchip multi-
codec machine driver.
And we need to add CONFIG_SND_SOC_RK3308 macro to ensure
compile correct on other SoCs that are without rk3308
codec.
Change-Id: I80d2ca5e269aa62865bd6b9f2da9fc7736bce4c9
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
The hpdet_jack should be set from external machine
driver.
Change-Id: I5f7e154c084434fa730c2a9ff505bfaa4e404a5f
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This patches fixes comparison between signed and unsigned values.
Change-Id: Ie417fdb8092463890a67bce7efa11f3ef20d5871
Signed-off-by: William Wu <william.wu@rock-chips.com>
When CONFIG_PM_SLEEP is disabled, we get a warning about
unused functions:
drivers/phy/rockchip/phy-rockchip-inno-usb2.c:1828:12: warning:
'rockchip_usb2phy_low_power_enable' defined but not used
Marking it as __maybe_unused avoids the warning without introducing
an ugly #ifdef.
Change-Id: I644b00eb2b30d9e4b63da46b7f387a7571b0f103
Signed-off-by: William Wu <william.wu@rock-chips.com>
When change vop status and ddr frequency at the same time,
the following deadlock will happen:
vop no/off dmcfreq
vop_crtc_disable update_devfreq
->mutex_lock(&vop->vop_lock); ->mutex_lock(&pd->pmu->mutex);
->pm_runtime_put(vop->dev); ->mutex_lock(&vop->vop_lock);
->mutex_lock(&pd->pmu->mutex); ...
Use new dmcfreq rwsem to decouple vop and pd driver, and get better
parallelism.
Change-Id: I56a4ee944200826d2a09e3ae8d2f4837f6f769d6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
When change vop status and ddr frequency at the same time,
the following deadlock will happen:
vop no/off dmcfreq
vop_crtc_disable update_devfreq
->mutex_lock(&vop->vop_lock); ->mutex_lock(&pd->pmu->mutex);
->pm_runtime_put(vop->dev); ->mutex_lock(&vop->vop_lock);
->mutex_lock(&pd->pmu->mutex); ...
By set dmc_nb.priority lower than vop to make sure pd notified after vop
to avoid deadlock.
Change-Id: I3ad147e7f5510f2b617efb600b97d8eb5849ee01
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
crypto and dmac share the same noc clk,
so mark the aclk_dmac1 as critical clk.
Change-Id: I34a4a7cc532a385086679fafb961a47b0a6abc3b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
crypto and dmac share the same noc clk,
so mark the aclk_dmac_bus as critical clk.
Change-Id: I02ccdbcb1ce50216daf2578538c8cfee9f6dd9d2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
crypto and dmac share the same noc clk,
so mark the aclk_dmac_bus as critical clk.
Change-Id: Ib0b70bbed3fdefeab7b6f2b5f88350a416e66787
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
On rockchip devices vbus is supplied by a separate power supply,
often through a regulator. Add support for describing the regulator
in device-tree following the same convention as several other usb phy's.
Change-Id: Ib13fa5d9c50cab3dd6711f2e7dd8489a4f06840b
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
(cherry picked from commit 9d685ed77b)
Most newer Rockchip SoCs provide the possibility to use a usb-phy
as passthrough for the debug uart (uart2), making it possible to
for example get console output without needing to open the device.
This patch adds an early_initcall to enable this functionality
conditionally via the commandline and also disables the corresponding
usb controller in the devicetree.
Currently only data for the rk3288 is provided, but at least the
rk3188 and arm64 rk3368 also provide this functionality and will be
enabled later.
On a spliced usb cable the signals are tx on white wire(D+) and
rx on green wire(D-).
The one caveat is that currently the reconfiguration of the phy
happens as early_initcall, as the code depends on the unflattened
devicetree being available. Everything is fine if only a regular
console is active as the console-replay will happen after the
reconfiguation. But with earlycon active output up to smp-init
currently will get lost.
The phy is an optional property for the connected dwc2 controller,
so we still provide the phy device but fail all phy-ops with -EBUSY
to make sure the dwc2 does not try to transmit anything on the
repurposed phy.
Change-Id: Ia9eed5b2b83d88fbeb7aabced689b21f4ea0ca69
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
(cherry picked from commit 605df8af33)
Deleted phy operations for rk336x and rk3399, because they
use Inno USB2.0 PHY, and we have added a new phy driver for
them. This can make our phy driver to stay closer to upstream.
Change-Id: I3b70cd78564c6a9873be88fc19954a8c2f95dd98
Signed-off-by: William Wu <william.wu@rock-chips.com>
It is not necessary to lock/unlock dmcfreq->lock on rockchip_dmcfreq_target.
update_devfreq call target callback with devfreq->lock.
So use rockchip_dmcfreq lock to serializes access to video_info_list only.
Change-Id: I9abd5fa1dfc37740d3fac9983775028dc14b64b5
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
The default state of pwm2 pin is a pull up, we need to keep it
for the second global reset issue, when pwm2 used for the regulator.
Change-Id: Ibe3487904196464114622dbc10ba270e3cf509d4
Signed-off-by: David Wu <david.wu@rock-chips.com>
This patch fixup that the wrong position when dma desc status
is DONE. even if the desc status is DONE, it is still able to
get the position from the dma driver. so, just remove the judgement.
Change-Id: I40e92bae09a002f4f5f0b2fab8b0e99fd3ee269d
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Enable dmc and dfi nodes to support ddr frequency
scaling on rk3288-evb-linux board.
Change-Id: I578b7dcace09a337abf9c7f640786db588ff9406
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Add dfi and dmc nodes in the device tree for the ARM rk3288 SoC.
To support ddr frequency scaling function, we need enable dmc and
dfi nodes.
Change-Id: I2ec7c216647443ec4354d282fd8f321f9d399929
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
This patch adds needed nodes for trust in rk3288-linux:
1.Add psci v1.0 support to call into secure world
through psci APIs.
2.Use non-secure dmac instead of secure one.
3.Use new efuse compatible to match secure interface
when kernel is in no-secure mode.
Change-Id: Id7fda3144388661979149cfa00822106b2872712
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
