Since storage drivers register in module_init, So the vendor_storage
should be initiated after it.
Change-Id: Icefce56c54713dd56ef992ec527e65fce4f0c977
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Item size is calculated according to the actual space used
Change-Id: I7133368130689f792f05e82fea04ebf16a755a37
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
When internal DMA ready, the last spare data may still in fifo.
Change-Id: I1cf670d2008ea62b67b517641e31386fd0877417
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Requesting perst# as high and then drive it low makes some
buggy devices fail to work properly, for instance Biwin SSD.
It's not mandatory to have a high-low transition for perst#
before powering up. So we request it as output-low state directly
and remove redundant code.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ib62954f8dccc8a21dd06e7a582263bcf62995f29
The resolution below 4K-60/50Hz don't support YUV420. If switch from
4K-60/50Hz in YUV420 to lower resolution may cause display err.
So if resolution below 4K-60/50Hz, color format should be
RGB/YUV444/YUV422.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ib96303f3bef1a1b269a9ac8845951b6a895ec5b8
Set resolution to 4K when connect an HDMI2.0 monitor
will enable scrambler feature.
At this time, change to connect an hdmi1.4 monitor will
cause black screen because we do not set scrambler feature bypassed.
So fix this.
Change-Id: Ic14b683719c8234c316dc1cacaa62c72a38e0294
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
to Improve signal compatibility disable scamble when tmdsclk less than
340Mhz by default. and can enable it by define "scramble-low-rates;"
in dts file.
Change-Id: I0bd5d8e2ea4df065d84018615d4c39cac7ac441a
Signed-off-by: xuhuicong <xhc@rock-chips.com>
There is not need to set dev name without address.
Fixes: 76f27bdd76 ("drm: bridge: dw-hdmi: using extcon instead of switch")
Change-Id: I2c23e29ad8f7b4a0b05b2237ae319e14c69a1cb1
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
On rockchip platform, hdmi input format is YCbCr444 when output mode
is YCbCr422. Then the value of HDMI_TX_INVID0 on YCbCr422 is same as
the value of YCbCr444, both is 0x09/0x0b. This make enc_out_bus_format
stroed in struct hdmi_data is wrong, which is MEDIA_BUS_FMT_YUV8_1X24
or MEDIA_BUS_FMT_YUV10_1X30.
When android set enc_out_bus_format to YCbCr422, dw_hdmi_setup will be
called and logo will flash.
This patch use colorspace restored in HDMI_FC_AVICONF0 to distinguish them.
Change-Id: I6b913951b58fb47628617c11d6059bc1be4e370a
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
The configured value sets H13T PHY PLL to multiply pixel clock by the
factor in order to obtain the desired repetition clock. For the CEA
modes some are already defined with pixel repetition in the input video.
So for CEA modes this shall be always 0.
Change-Id: Iea4a00247f25c134dbd67ba77c00eb4393622385
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
On RK3328, dw-hdmi driver is reloaded after bind and unbind
then it will use the first register debugfs address if no run
debugfs_remove_recursive, and cause system crash.
Change-Id: Iafa6b4059962b62c79157a9cf6c3e1d56df48f03
Signed-off-by: Huicong Xu <xhc@rock-chips.com>
when other devices bind failed,drm will unbind and re-bind all devices.
if don't cancel the delayed work but flush and destroy workqueue directly,
kernel point is likely to become NULL.
Change-Id: Ib48704186ee298cbd4daac1cdbbac5fb3906b6bb
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Default value of hdmi->colordepth is defined by input color mode,
so there is no need to set value again when color depth property
is created.
Change-Id: I2e242fabdaadc0c3b41e48f806cbded5f619c455
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Filling in the missing parts from:
'commit d7f22ab4c1 ("drm: bridge: dw-hdmi: fix wrong color if get
edid error at bootup")'
Change-Id: I92b690dcc332e9f9e50ef7d457734952a9f1ef2a
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
To differentiate extend colorimetry and normal colorimetry, we
add the offset HDMI_COLORIMETRY_EXTENDED in colorimetry property.
It should use same value in dw_hdmi_rockchip_select_output.
Change-Id: I13e10b6e8211e7a2634dbd4b6c5310bc129bfa8d
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
When 4K x 2k 60Hz/50Hz tmds clock is above the max tmds clock, setting its
color to YUV420. A few TV edid declare that they can't support
4K x 2k 60Hz/50Hz YUV420, we still set color to YUV420 or 4K x 2k 60Hz/50Hz
tmds clock will over the limit.
Change-Id: Id57c9313ab52973927c578d0eb2a7b1b30cb9ec1
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
First, write hdcp key by "ProvisioningTool" if you want to
enable hdcp function, or else will auth fail.
To check whether the hdcp is enable or not
#cat /sys/class/misc/hdmi_hdcp1x/enable
0:hdcp is disabled
1:hdcp is enabled, hdmi screen will be pink if it is failed;
2:hdcp is enabled, hdmi screen will be normal if it is failed;
Enable or disable hdcp function
#echo 0 > /sys/class/misc/hdmi_hdcp1x/enable
#echo 1 > /sys/class/misc/hdmi_hdcp1x/enable
#echo 2 > /sys/class/misc/hdmi_hdcp1x/enable
Get the status of hdcp
#cat /sys/class/misc/hdmi_hdcp1x/status
The result will be one of the follow list:
hdcp disable;
hdcp_auth_start
hdcp_auth_success;
hdcp_auth_fail;
unknown status.
Change-Id: Iac6c7d6a1196ce9cf2869d7916bbe6c8941ec13b
Signed-off-by: Huicong Xu <xhc@rock-chips.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Hdmi suspend or resume may be called before hdmi initialization. We must
verify that hdmi is initialized first.
Change-Id: I2a680209e64b9c1aebc2d9ee19d543927137afd0
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
If HDMI HPD detect delayed work won't be cancel, system will
crush because clk and PD has been disabled. So HDMI HPD detect
workqueue should be flushed when system suspend.
Change-Id: Idb8018c2efcffc3aee5fd80872f1270360809235
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
If edid can't be got when hdmi plug in, hdmi color depth mask and format
won't be updated. The color list in the setting are those of the previous
TV. This commit fix the error.
Change-Id: I5ed4be5efa2a69be0b58489f58a3af5de9912292
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
According to HDMI 1.4b specification: If the transmitted video
format has timing such that the phase of the first pixel of
every Video Data Period corresponds to pixel packing phase 0
(e.g. 10P0, 12P0, 16P0), the Source may set the Default_Phase
bit in the GCP. The Sink may use this bit to optimize its filtering
or handling of the PP field.
This means that for 10-bit mode the Htotal must be dividable by 4;
for 12-bit mode, the Htotal must be divisible by 2.
Change-Id: I02e632d095141cbabcba06dc1321ae0dc69dc736
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
When the color depth is 24 bits per pixel video, the CD
field in General Control Packet should be "Color Depth
not indicated", then the colordepth in register vp_pr_cd
& csc_scale should assign to zero.
BUG=chrome-os-partner:38212
TEST=speedy board, Test with Agilent Technologies U4002A
HDMI Protocal Analyzer
Change-Id: Ifd5767d339fdbff11e234ec0891c8f3df1dd66a5
Reviewed-on: https://chromium-review.googlesource.com/261850
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Yakir Yang <ykk@rock-chips.com>
Commit-Queue: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Formula3 and Formula2 for csc decimation will cause hdmi yuv422
display err.
Formula3:
The pixel color of left 0-14 columns and right 0-12 columns is
err.
Formula2:
The pixel color of left 0-2 columns is err.
Change-Id: I94fdd5fd962a24fde02dde1fe3ac10437ad117ad
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Under following processes, rxsense will be not match the real
signal status.
1. HDMI plug in, irq is triggered.
2. HDMI irq is mute in dw_hdmi_hardirq, bring up dw_hdmi_irq.
3. For HDMI connection is not stable, phy_stat read in
dw_hdmi_irq may be zero, then hdmi->rxsense will be false.
4. Connection fallback to stable, but dw_hdmi_irq had not
unmute the irq, irq is not triggered again, and hdmi->rxsense
keep false.
5. repo_hpd_event inform HDMI is pluggned in, dw_hdmi_bridge_enable
is called to enable HDMI. For rxsense is flase, bridge is not
powered up.
When repo_hpd_event is called, we think HDMI connection is stable,
updating rxsense is reliable.
Change-Id: Ie1f52f65b15e9a603dad9200529202053528a390
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Introduce status node in debugfs to show HDMI output status,
such as phy status, color and eotf.
Here is a sample log:
PHY enabled Mode: HDMI
Pixel Clk: 594000000Hz TMDS Clk: 594000000Hz
Color Format: YUV422 Color Depth: 10 bit
Colorimetry: ITU.BT2020 EOTF: ST2084
x0: 0 y0: 0
x1: 0 y1: 0
x2: 0 y2: 0
white x: 0 white y: 0
max lum: 0 min lum: 0
max cll: 0 max fall: 0
Change-Id: I5d458b633dd3bd9aab67cc91f1695621937e58f5
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This reverts commit 384134cb60.
bcm2079x is unused.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ibbc1b18fbadc1de9fa66915348b3382533ad1621
For compatibility with GKI, drm_display_mode_from_vic_index() can't
be export function. So we use default mode list when edid can't
be got.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ic7d046e4ccf36981449d36067efd8bb2388e27e4
msgs[0].addr will be 0x30 when read edid with more than 2 block.
but still a read edid operation with write DDC_ADDR to
HDMI_I2CM_SLAVE register.So fix it.
Change-Id: I5f0cd9172acd4a68d5b54eaf99f17b45385a4263
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
To set dw hdmi i2c bus adapter scl clock rate, we introduce two device
tree parameter, ddc-i2c-scl-high-time-ns and ddc-i2c-scl-low-time-ns.
ddc-i2c-scl-high-time-ns: how many ns SCL hold high
ddc-i2c-scl-low-time-ns: how many ns SCL hold low
After measurement, 50KHz scl clock rate recommended configuration is:
&hdmi {
ddc-i2c-scl-high-time-ns = <9625>;
ddc-i2c-scl-low-time-ns = <10000>;
};
100KHz recommended configuration is:
&hdmi {
ddc-i2c-scl-high-time-ns = <4708>;
ddc-i2c-scl-low-time-ns = <4916>;
};
If dts parameter is not available, the default scl rate is 100KHz.
Change-Id: I6f6b0bf1694ab59e70da789ead99e15a53c93e4d
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This patch add hdmi_output_colorimetry to support modify
hdmi output colorimetry. It could be following value:
- None
- IUT_2020
Default value is None, which means normal hdmi output
colorimetry.
Change-Id: Ib4883fd0553d9d4193c7295812d2c1433724fe63
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
there are maximum TMDS clock limit, when the clock is out of range
reducing frequency by set color format to yuv420 and/or set color
depth to 8bit
Change-Id: I8b79de97329561bf0399d05c0264a5c818f844fc
Signed-off-by: Huicong Xu <xhc@rock-chips.com>
If color depth is automatic, it is same as 8bit.
If tmdsclk > max_tmds_clock, fall back to 8bit.
Change-Id: Ia8cbf5206831ef99456ae59add94c6f8b5a33380
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
