support more cpu freq
add armcore div setting
Change-Id: I46ab974da763bab2e887377848be1d9049a1568f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add a ddrc clock into clk branches, so we can do ddr frequency
scaling on rk3288 platform in future.
Change-Id: Ia6c93e5ce82fa30475eddf051bc9ea2512b0cc07
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Compiling the DT file with W=1, DTC warns like follows:
Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property
Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Change-Id: I5748be7888db149633c3980c3f5e9715cd256a52
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Compiling the DT file with W=1, DTC warns like follows:
Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property
Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Change-Id: Id239f49618a818ad87bb77e99f52b52a5ee2dbc6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Extend timeout value from 100 jiffies to 1000 millisecond.
Change-Id: I4941bb487051a73cf348f72799226e17d4b60e49
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
fixup the scale calculation formula on the case
src_height == (dst_height/2).
Change-Id: I620a4646232c016ff1547b5b6469ed2eedeacfed
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
There is a bug of pll lock detection in previous code.
/* Wait for PHY PLL lock */
msec = 5;
do {
val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
if (!val)
break;
...
} while (1)
while is break if pll is not lock yet, the real lock status may
be after the dw_hdmi_enable_video_path.
This bug is fixed in commit <a479fa5417b12fdf7aef8e41fdb99393e1c28581>
(FROMLIST: drm: bridge: dw-hdmi: Fix the PHY power up sequence)
But it introduced an new bug: hdmi output timing may be not stable,
the format shown on some TV is not a standard hdmi timing. For example,
1080P will be shown as 1922x1080 on LEADSTAR LD-1088.
After reorder the HDMI Initialization Step, phy initialization is
moved after the dw_hdmi_enable_video_path, this bug is fixed.
Change-Id: Id996978ceabcf1cce4bf83ddb84528c04fbb7583
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
The function is_rockchip isn't used any more now that phy reset
operation is performed based on detected phy type.
Change-Id: I58e7a222bc1e1578f0d5d2fcd884b17171fb9601
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
DWC HDMI 2.0 TX PHY has the same register layout with DWC HDMI
MHL TX PHY, so we use hdmi_phy_configure_dwc_hdmi_3d_tx as
DW_HDMI_PHY_DWC_HDMI20_TX_PHY default configuration function.
Change-Id: Ib50464b9eef87707a8597493cc05e61a1ecde240
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Because init.rc does the following operation, handle_sysrq
will do nothing. If we want to use sysrq, __handle_sysrq
can work.
write /proc/sys/kernel/sysrq 0
Change-Id: Ia51debd92f393326f183736e405e25dc4d6a2abc
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
msgs[0].addr will be 0x30 when read edid with more than 2 block.
but still a read edid operation with write DDC_ADDR to
HDMI_I2CM_SLAVE register.So fix it.
Change-Id: I5f0cd9172acd4a68d5b54eaf99f17b45385a4263
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Because optee works on both kernel 3.10 and 4.4, these two branches
have different rockchip sip protocol that sip version v1 for 3.10
and sip version v2 for 4.4
Change-Id: I4f69352d2001b1c22c5617dc443510263b4c53f5
Signed-off-by: chenjh <chenjh@rock-chips.com>
because gpio framework doesn't print any related info
Change-Id: I2325270027210432cd31d1cec6caf19770363705
Signed-off-by: chenjh <chenjh@rock-chips.com>
The PHY requires us to wait for the PHY to switch to low power mode
after deasserting TXPWRON and before asserting PDDQ in the power down
sequence, otherwise power down will fail.
The PHY power down can be monitored though the TX_READY bit, available
through I2C in the PHY registers, or the TX_PHY_LOCK bit, available
through the HDMI TX registers. As the two are equivalent, let's pick the
easier solution of polling the TX_PHY_LOCK bit.
The power down code is currently duplicated in multiple places. To avoid
spreading multiple calls to a TX_PHY_LOCK poll function, we have to
refactor the power down code and group it all in a single function.
Tests showed that one poll iteration was enough for TX_PHY_LOCK to
become low, without requiring any additional delay. Retrying the read
five times with a 1ms to 2ms delay between each attempt should thus be
more than enough.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170305233539.11898-1-laurent.pinchart+renesas@ideasonboard.com
Change-Id: I64dadab663b34800d4fe3fe4fd9cd4fb029e2ce3
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9604811/)
The PHY reset signal is controlled by bit PHYRSTZ in the MC_PHYRSTZ
register. The signal is active low on Gen1 PHYs and active high on Gen2
PHYs. The driver toggles the signal high then low, which is correct for
all currently supported platforms, but the register values macros are
incorrectly named. Replace them with a single macro named after the bit,
and add a comment to the source code to explain the behaviour.
The driver's behaviour isn't changed by this rename, the code will still
need to be fixed to support Gen1 PHYs.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-19-laurent.pinchart+renesas@ideasonboard.com
Change-Id: I61a1185dc2528f6be61a3f250902445b92217365
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry pick from 54d72737b0)
The DWC HDMI TX can be recognized by the two product identification
registers. If the registers don't read as expect the IP will be very
different than what the driver has been designed for, or will be
misconfigured in a way that makes it non-operational (invalid memory
address, incorrect clocks, ...). We should reject this situation with an
error.
While this isn't critical for proper operation with supported IPs at the
moment, the driver will soon gain automatic device-specific handling
based on runtime device identification. This change makes it easier to
implement that without having to default to a random guess in case the
device can't be identified.
While at it print a readable version number in the device identification
message instead of raw register values.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-14-laurent.pinchart+renesas@ideasonboard.com
Change-Id: Iaa8e17429e9b4033f97b2bf49504e6f390ce7c44
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry pick from 0527e12e82)
1. add lvds node to /display_subsystem;
2. set route_mipi state to closed at rk3368-android.dtsi
3. set route_mipi state to okay at rk3368-sheep.dts
Change-Id: I8052e38764f85f700014ea40b208b38c09cae56b
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
I found if eDP_AVDD_1V0 and eDP_AVDD_1V8 are not been power at
RK3288, once trying to enable the pclk clock, the kernel would dead.
This patch would try to enable them first.
The eDP_AVDD_1V8 is used for eDP phy, and the eDP_AVDD_1V0 are used
both for eDP phy and controller.
Change-Id: I4e8a34609d5b292d7da77385ff15bebbf258090c
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Randy Li <randy.li@rock-chips.com>
If the temperature(sbs-battery) reaches the switch_on_temp, it would try
to calculate requested power of all thermal instances. Then hit the
crash[0] caused by the gpu thermal sensor, since the thermal driver had not
registered in time.
[0]
[ 0.827943] Call trace:
[ 0.827953] [< (null)>] (null)
[ 0.827969] [<ffffffc00070af1c>] get_static_power+0xd8/0xe8
[ 0.827981] [<ffffffc00070b190>] devfreq_cooling_get_requested_power+0x94/0x170
[ 0.827997] [<ffffffc0007094c8>] power_allocator_throttle+0x270/0x804
..
Change-Id: I63f66e54d69115165a7b3ec798b9009c360daa62
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
