the deskew fifo works on its own pointers may cause inter-lane skew
to exceed the vesa standard, this poses a risk of errors in dp sink
parsing MSA packet which inserted in data stream
Change-Id: Ia3bdfaed8696c8f7f21f39f0b55d18b1dce7761f
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
For a more stable system, delete the 528MHz frequency and open
the 666MHz frequency ODT.
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I0354c6dde8f39a9b41878446475ee3acbe1be729
Fixes: 6bd92608df ("drm/rockchip: drv: get acm and csc info when boot")
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I0dd41b229fce0c85bd3df03f03b4b40da06ef53a
After other threads will trigger the wakeup, there may be a case where
the request is exited abnormally, so it is necessary to wake_up again
when the function exits.
Change-Id: Ia3e754cf3d4f9064ddc07a590f73f2f75c92d2c3
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Amends ln0/ln2 RX DFE to improve the compatibility of USB3 link training.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I568f9260bcfbb4625139222f06b68765f187dd04
The camera device should keep *power on* until stream off, that make
sure the mclk is enable.
Signed-off-by: yuefu.su <yuefu.su@rock-chips.com>
Change-Id: I877d73cfa64e484e7c93e7b761d31ff23e353960
The session can only be released after all tasks are released.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I9a4e7940323be72cb0982338777af813888f957f
regulator should always on when system suspend, avoid wifi crash.
Change-Id: If78702e56b68f653b2d50a06d7fd31bc4ced2943
Signed-off-by: Xu Xuehui <xxh@rock-chips.com>
The touchscreen i2c is abnormal due to current crosstalk of lcdc
d18~23,so reduced drive strength reduces crosstalk
Change-Id: Iaa7f6fc3854ecf2ab5e96d96c44464044a23b128
Signed-off-by: Lin Jianhua <linjh@rock-chips.com>
DP firmware uses fixed phy config values to do training, but some
boards need to adjust these values to fit for their unique hardware
design. So get phy config values from dts and use software link training
instead of relying on firmware, if software training fail, keep firmware
training as a fallback if sw training fails.
Change-Id: I075bff6aa153a5e18b6a5ddec2645131f1411913
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
The drm_dp_link is removed. And link.num_lanes is instead by
max_lanes. Link.rate is instead by max_rate.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I95cbaa541bdf28133ab86f46ce3ac9f0903d364d
Use wait_event_interrupt to replace wait_event_timeout.
The task irq or task work timeout will wake up the session wait.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I47254ca0e66b210d91578b24d63578f9ea5308f9
On the RK3562 SoC, the HPLL is designed dedicated for audio.
This patch assigns PLL_HPLL as the parent of digital audio
interface default. and Set PLL_HPLL to 983.04M(48k group)
default to achieve better jitter performance.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I21615ae46209a2be31630987350131abd3b33a97
Currently, the BCLK/FSYNC enable is addressed in hw_params
stage, because the real clk is measured by samplerate. so,
it is quite a good solution.
But, on the system PM situation, it is failed to recovery
BCLK/LRCK after resume. the root cause is that never do
'hw_params' after resume. which is similar to XRUN issue.
So, let's move it to prepare stage which any path must do
before trigger-start.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I9025a98259a4e9bd9f09ec3d23584f753552031d
This patch use the generic pm_runtime_force_* API for system PM,
because both of them do the same action. let's make it implemented
with runtime PM.
Ref: commit 37f204164d ("PM: Add pm_runtime_suspend|resume_force functions")
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ice5057ca5cdf8999990283a99921b7b6a30cd557
1. NV12/NV16/YUYV xoffset must aligned as 2 pixel;
2. NV12/NV15 yoffset must aligned as 2 pixel;
3. NV30 xoffset must aligned as 4 pixel;
4. NV15/NV20 xoffset must aligend as 8 pixel at rk3568/rk3588/rk3528/rk3562,
others must aligned as 4 pixel;
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I28d69d1f8189963170ef798c12bfd60fb092ef20
