Commit Graph

1274498 Commits

Author SHA1 Message Date
Wenping Zhang
20e277459e net: wireless: rockchip_wlan: Add missing BH locking around __napi_schdule()
The following errors are seen when wifi is running:
NOHZ tick-stop error: Non-RCU local softirq work is pending, handler #08!!!

Fix this problem by adding the BH locking around __napi_schedule, in the same way
it was done in commit e63052a5dd ("mlx5e: add add missing BH locking around napi_schdule()").

Change-Id: I25544b52460639ba95d3cbdd9644ab95f01a2654
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>
2024-09-24 20:37:18 +08:00
Zhong Shengquan
b0ca1b7b89 ASoC: rockchip: asrc: Fix asrc get parent clock error
Fix the if condition logic in the rockchip_asrc_get_clk_parent
function by replacing the third "&&" with "||".

Change-Id: Ib5c00812bb72c0443ea9565e8d669f7a7fafd156
Signed-off-by: Zhong Shengquan <shengquan.zhong@rock-chips.com>
2024-09-24 18:35:00 +08:00
Finley Xiao
38724c75e9 clk: rockchip: rk3506: Remove CLK_IS_CRITICAL flag for v1pll
Change-Id: I3e4074cbcb15e7ff43238bbd22727109b32b1005
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2024-09-24 17:51:36 +08:00
Finley Xiao
3ffefedf76 clk: rockchip: rk3506: Make clk_ddrc critical
Change-Id: I88cd8b72e6667bd95193363b26c9d1d31e9295ea
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2024-09-24 17:51:36 +08:00
Zheng zhiqi
db84683134 arm64: dts: rockchip: rk3576-vehicle-evb-v20: enable saiX
1. enable sai1 for TDM card
2. enable sai2 for BT card
3. enable sai4 for FA caard
4. enable spidev0.0 for audio control

Change-Id: Ib9a20936164d5ce5d82ba1736001c66eeaaa8b68
Signed-off-by: Zheng zhiqi <looper.zheng@rock-chips.com>
2024-09-24 16:48:39 +08:00
Algea Cao
cb42b8db86 drm/bridge: synopsys: dw-hdmi-qp: Check that necessary hdmi clock is on when hdmi bind
Check whether ipi/link/vid clk is enabled in
uboot to determine whether the uboot logo is
enabled.

Change-Id: I6da4b0694a3df5a48136c96fa21d5f98dcc8d7c7
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2024-09-24 14:08:38 +08:00
Finley Xiao
a5e94c5ae1 ARM: dts: rockchip: rv1106: Remove otp arb and pmc clock
Change-Id: I679f1de9961c19f3d8726b4c709d231e46d26838
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2024-09-23 19:51:23 +08:00
Finley Xiao
cb2e07986b arm64: dts: rockchip: rk3562: Remove otp arb clock
Change-Id: I3d9e5a72c5fe218bd5d16499b301d112f8f7d133
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2024-09-23 19:51:23 +08:00
Finley Xiao
e4366b6b62 arm64: dts: rockchip: rk3588s: Remove otp arb clock
Change-Id: If557c82d9a51190670cd873a18cd435e84878128
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2024-09-23 19:51:14 +08:00
Finley Xiao
9afefeba8a clk: rockchip: rv1106: Remove clk_pmc_otp and clk_otpc_arb
Fixes: 73d255eb3b ("nvmem: rockchip-otp: do not close common clk")
Change-Id: I7b73ac1e87bcdab04471eb8805f58fc6a438d7a4
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2024-09-23 18:20:37 +08:00
Finley Xiao
993c9c6625 clk: rockchip: rk3562: remove clk_otpc_arb
Fixes: 73d255eb3b ("nvmem: rockchip-otp: do not close common clk")
Change-Id: I719526a754bebbc705c6e283d014e8a7000de3ca
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2024-09-23 18:20:37 +08:00
Finley Xiao
353ab48958 clk: rockchip: rk3588: Removd clk_otpc_arb
Fixes: 73d255eb3b ("nvmem: rockchip-otp: do not close common clk")
Change-Id: I470ec453b67aca985dc04f31897ccab86f12d8ad
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2024-09-23 17:34:36 +08:00
Jianwei Zheng
4849e6cab6 usb: dwc2: fix dwc2 resume failed when device is connected
Current code if the device is connected and do _dwc2_hcd_resume(),
it will goto unlock and exit this function, cause some dwc2
controllers that does not support Partial Power Down mode resume
failed and perform the following error log:

    usb 2-1: reset high-speed USB device number 2 using dwc2
    usb 2-1: device descriptor read/64, error -110
    usb 2-1: device descriptor read/64, error -110

Fixes: c74c26f6e3 ("usb: dwc2: Fix partial power down exiting by
system resume")
Change-Id: I34d449f1286c8122883aedcd830f2744f1a2267d
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
2024-09-23 16:57:00 +08:00
Guochun Huang
8dd21a945d phy: rockchip: mipi-dcphy: limit the maximum addr according to DC-PHY register map
Fix the issue where the system will reboot when exporting the PHY
registers from user space through the following command:

cat /d/regmap/feda0000.phy-dcphy/registers

or

cat /d/regmap/fedb0000.phy-dcphy/registers

Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I46f90a04d15a4e583238e966953bc70fb9c3c150
2024-09-23 16:56:16 +08:00
Cai YiWei
353a8c61a1 media: rockchip: isp: fix isp39 unite stats frame id
Change-Id: I18b6b0109098576f898e07de29df24f797faf9d2
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
2024-09-23 09:36:52 +08:00
Yifeng Zhao
63d2f83cdc soc: rockchip: sdmmc_vendor_storage: fix the issue of inaccurate calculation of free size
When the amount of data written increases, more space is allocated,
but when the amount of data written decreases, the allocated space
is reclaimed without updating the value of free_size.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Iecf2af482c1e8af35b9fa3227bcbb597d75f770d
2024-09-20 19:56:32 +08:00
Frank Wang
f4fdb8d83f usb: typec: tcpci: husb311: fix tx failure
Since the hardware bug of HUSB311, its TX fifo become abnormal
when plug in a PD charger after plug out the cable from the PC.

As a workaround, we do ResetTransmitBuffer after each TX packet
is finished to prepare for the next.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Ieebd090879a45ee2b5a1720e3debf860712e162c
2024-09-20 14:08:46 +08:00
Zheng zhiqi
f1a9ea8906 arm64: dts: rockchip: rk3576-vehicle-evb-v20: open spi dev
Open spi0:0 dev for audio, control adsp

Change-Id: Ib7c3e3de33b0567b15a43899c43ed637b54aabca
Signed-off-by: Zheng zhiqi <looper.zheng@rock-chips.com>
2024-09-20 09:19:40 +08:00
Sandy Huang
44ccff798b drm/bridge: synopsys: dw-hdmi-qp: add mode covert at dual_connector_split
At split mode or dual connector split, the mode of horizontal direction
must x2.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I4583cb575c6714796b63c3dc312eb3c23319b116
2024-09-19 11:03:20 +08:00
Finley Xiao
885afdcd0e PM / devfreq: rockchip_dmc: Fix dev_pm_opp_get_opp_table() return value
Change-Id: I8a3f293bdfc17574735365e5049bdf47ce321770
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2024-09-19 10:55:47 +08:00
Finley Xiao
8ceb525d09 soc: rockchip: opp_select: Fix dev_pm_opp_get_opp_table() return value
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I2f3b2bb6ccf359574a0b8d503f3491d9fa7e2299
2024-09-19 10:33:24 +08:00
Finley Xiao
b6c6cd2b3a soc: rockchip: system_monitor: Fix dev_pm_opp_get_opp_table() return value
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ia1db3e6087f57c4d804da779059584c56610e9ef
2024-09-19 10:31:56 +08:00
Ye Zhang
faaec9bb5d ARM: dts: rockchip: rk3506: set DS of pwm pins to level1
According to SI report, the default driver strength should be level1.

Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I2d10de82d9b836a479b38b782732a95f79079deb
2024-09-18 17:30:32 +08:00
Ye Zhang
87108d5ab4 ARM: dts: rockchip: rk3506-pinctrl: Fix driver strengths of some SPI IOs
Fixes: 68cf3d9c46 ("ARM: dts: rockchip: rk3506-pinctrl: Increase driver strengths of some SPI IOs")
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I0e0d75ab72b0a80853437cb9c2dde53bc87c8dd3
2024-09-18 17:30:21 +08:00
Zain Wang
38049431f3 ARM: configs: rk3506: Separate modules configs from defconfig
Separate modules:
1. rk3506-display.config
2. rk3506-ethernet.config
3. rk3506-wifibt.config
4. rk3506-usb-host.config
5. rk3506-usb-peripheral.config
6. rk3506-usb-otg.config

Keep 'm' value to these modules in rk3506_defconfig.

Change-Id: I74d77a29ed6e133e45f1a8cf1c7e9ca46509fe21
Signed-off-by: Zain Wang <wzz@rock-chips.com>
2024-09-18 17:16:44 +08:00
Zain Wang
b3b9046ec5 usb: dwc2: fix compile error in USB_DWC2_HOST mode
If enabled CONFIG_USB_DWC2_HOST, we will get error:

drivers/usb/dwc2/platform.c: In function ‘dwc2_resume’:
drivers/usb/dwc2/platform.c:825:12: error: ‘struct dwc2_hsotg’ has no member named ‘driver’
  825 |   if (!dwc2->driver)
    |            ^~

This is the code for periperal mode, add a macro to
remove them from CONFIG_USB_DWC2_HOST.

Change-Id: Ib2b9622d5cfe5e4c9329030fa10e0635b1aa7fb8
Signed-off-by: Zain Wang <wzz@rock-chips.com>
2024-09-18 17:12:07 +08:00
Guochun Huang
db4eb2bcf1 drm/rockchip: dp: extcon sync for audio in .loader_protect helper
Type: Fix
Redmine ID: #506052
Associated modifications: gerrit links
 Test: test method

Change-Id: I114679d477f33f0a6d8b13d0f72d9c36c41fc40c
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
2024-09-18 14:05:13 +08:00
Guochun Huang
0e7febeb4a drm/rockchip: drv: mv show logo after drm_dev registered
execution of extcon_set_state_sync() within the DP driver’s
.loader_protect helper failed due to dp->audio->extcon not
being allocated in dw_dp_single_audio_init() yet, which resulted
in the audio not work when the power-on logo feature is enabled.
so mv drm_dev_register() before rockchip_drm_show_logo().

Call trace:

  dw_dp_single_audio_init+0xc8/0x194
    dw_dp_encoder_late_register+0x28/0xa8
      drm_encoder_register_all+0x40/0x5c
	drm_modeset_register_all+0x38/0x7c
	  drm_dev_register+0x264/0x2e0
	    rockchip_drm_bind+0x1ec/0x2c8

Type: Fix
Redmine ID: #506052
Associated modifications: gerrit links
Test: test method

Change-Id: I1109a5ed90ac1c36028e050c41349c316d74e859
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
2024-09-18 14:04:51 +08:00
Damon Ding
b6270dfe78 drm/rockchip: rgb: add dclk delayline configs for rk3506
Remove redundant parameter passing for 'dclk_delayline', and dclk
delayline configs may be different between bt1120/bt656 and rgb
display interface.

Change-Id: I77b78665a1403ad9d39929b39811069f0ecc130e
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
2024-09-18 10:16:58 +08:00
Yandong Lin
22c5e525ac video: rockchip: mpp: add devices load statistics
1.The default statistical time is 0, means the load statistics function
is disabled.
If want to enable the function, need echo a valid value to
load_interval.
e.g. 1000ms:
$echo 1000 > /proc/mpp_service/load_interval

2.show load info:
rk3588_t_evb7:/ # cat /proc/mpp_service/load
fdb51000.avsd-plus        load:   0.00% utilization:   0.00%
fdb50400.vdpu             load:   0.00% utilization:   0.00%
fdb50000.vepu             load:   0.00% utilization:   0.00%
fdb90000.jpegd            load:   0.00% utilization:   0.00%
fdba0000.jpege-core       load:   0.00% utilization:   0.00%
fdba4000.jpege-core       load:   0.00% utilization:   0.00%
fdba8000.jpege-core       load:   0.00% utilization:   0.00%
fdbac000.jpege-core       load:   0.00% utilization:   0.00%
fdbb0000.iep              load:   0.00% utilization:   0.00%
fdbd0000.rkvenc-core      load:  97.56% utilization:  93.45%
fdbe0000.rkvenc-core      load:  97.33% utilization:  92.51%
fdc38100.rkvdec-core      load:   0.00% utilization:   0.00%
fdc48100.rkvdec-core      load:   0.00% utilization:   0.00%
av1d-master               load:   0.00% utilization:   0.00%

Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I0b1c6d3efc7cd7708e7f367ad917b865db67a08a
2024-09-14 14:47:21 +08:00
Damon Ding
14dac2f903 ARM: dts: rockchip: rk3506g-evb1: fix pinctrl of rgb for mcu display board
Fix the pinctrl of rgb to 'mcu_rgb565_pins', because the driver
strength configs of rgb and mcu are different for rk3506.

Change-Id: I488cdfd13e42c862be0f8ecd10bab215e87e87b8
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
2024-09-13 15:49:55 +08:00
Damon Ding
af73c672cb ARM: dts: rockchip: rk3506: modify default DS level for vop pinctrl configs
According to SI report, default drive strength of vop pinctrl
configs should be improved as described below:

bt1120/bt656:
CLK              level4
DATA             level2

mcu:
RS/WEN/CS/REN    level2
DATA             level0

rgb:
CLK              level3
HSYNC/VSYNC/DEN  level2
DATA             level2

Add a set of pinctrl configs which named "mcu_*", because the
driver strength configs of rgb and mcu are different for rk3506.

Change-Id: Ide4dd04531d8760194ab745d2fb348c644f27c4f
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
2024-09-13 15:49:55 +08:00
Ye Zhang
4dc35e3247 thermal: rockchip: Add trim temperature for rk3576
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I6ba9a60fb389b12a6d63ea3b19e271cf9d5ecad5
2024-09-12 19:41:01 +08:00
Ye Zhang
3e7349667d arm64: dts: rockchip: rk3576: Fix trim configure for tsadc
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: Id7399f84a7d3f75213528c89151efe1862b1b02e
2024-09-12 19:40:42 +08:00
Sugar Zhang
2b6899e2d0 ASoC: rockchip: sai: Fix mclk check
Before:
rockchip-sai ff810000,sai: mismatch mclk: 12287999, expected 0 (+/- 5Hz)

After:
rockchip-sai ff810000,sai: mismatch mclk: 12287999, at least 24576000

Fixes: 1831ca1cdc ("ASoC: rockchip: sai: Fix mclk rate check")

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I7addcf70104515c50463a42fc9fd7fe46a9456fd
2024-09-12 18:08:29 +08:00
Sugar Zhang
f4e6d5530a ASoC: rockchip: sai: Add support lanes parsed from DT
used to assign lanes from DT.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I2064b201a8325e0b5d1e7a448a14345443a173a4
2024-09-12 18:08:29 +08:00
Zheng zhiqi
3fa1e010c7 arm64: dts: rockchip: rk3576-vehicle-evb: change sai1 channel
Change sai1 tx 3 lanes, rx 2 lanes

Change-Id: If3d87aeec5382ea7a55163cd97031dd196021ce9
Signed-off-by: Zheng zhiqi <looper.zheng@rock-chips.com>
2024-09-12 15:43:47 +08:00
Zheng zhiqi
e7d061526b arm64: dts: rockchip: rk3576-vehicle-evb-v20: change sai1 channel
Change sai1 tx 3 lanes, rx 2 lanes

Change-Id: If68d799789490fce0ecb5da55c4b9dbe1fa7591a
Signed-off-by: Zheng zhiqi <looper.zheng@rock-chips.com>
2024-09-12 15:43:47 +08:00
Zhen Chen
d1b62d2e45 MALI: rockchip: upgrade bifrost DDK to g25p0-00eac0, from g24p0-00eac0
mali_csffw.bin from Valhall DDK g25(r50) is included.

Change-Id: Ic454428c384456a14b29d9651f537eb59c11284d
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
2024-09-12 10:52:10 +08:00
Zhen Chen
4cedc115fd MALI: rockchip: upgrade bifrost DDK to g24p0-00eac0, from g22p0-01eac0
mali_csffw.bin from Valhall DDK g24(r49) is included.

Change-Id: Ic48b63e744457163fbae3f41b477fc2827a1380e
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
2024-09-12 10:52:10 +08:00
YouMin Chen
f8fff854d7 PM / devfreq: rockchip_dmc: ignore notifier during dmcfreq suspend
Do not allow changes to frequency and voltage after dmcfreq enter suspend.

Change-Id: Ide146cfd49d77ee7dff88bd3b9eeb2e5d2ec82c0
Signed-off-by: YouMin Chen <cym@rock-chips.com>
2024-09-12 10:13:05 +08:00
YouMin Chen
2961e8dde5 PM / devfreq: rockchip_dmc: update dmcfreq->volt in rockchip_dmcfreq_set_volt
Update dmcfreq->volt within the rockchip_dmcfreq_set_volt function to avoid
uninitialized use errors that may occur during rockchip_dmcfreq_resume().

Change-Id: I1fd3303df5adf2837b994b4fee31848864d4dccd
Signed-off-by: YouMin Chen <cym@rock-chips.com>
2024-09-11 19:44:58 +08:00
Xing Zheng
f981c02164 ARM: rk3506_defconfig: enable SND_PCM_TIMER by default
The plugins of dsnoop/dmix will be fault if this config is disable:
----
root@rk3506-buildroot:/etc# arecord -Ddefault -c 2 -r 16000 -fS16_LE /tmp/record.wav -vv
ALSA lib pcm_direct.c:1504:(snd1_pcm_direct_initialize_poll_fd) unable to open timer 'hw:CLASS=3,SCLASS=0,CARD=0,DEV=0,SUBDEV=1'
ALSA lib pcm_dsnoop.c:643:(snd_pcm_dsnoop_open) unable to initialize poll_fd
arecord: main:850: audio open error: No such file or directory

Therefore, we needs to enable it.

before:
   text	   data	    bss	    dec	    hex	filename
4934889	2270232	 114496	7319617	 6fb041	vmlinux
after:
   text	   data	    bss	    dec	    hex	filename
4944910	2272032	 114944	7331886	 6fe02e	vmlinux

Change-Id: I669e50141957546f35b3a0ede3e1b7928ca14b9c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2024-09-11 18:36:34 +08:00
Algea Cao
399bc0fb97 drm/rockchip: dw_hdmi: Set rk3588 hpd low level count threshold value to 2ms
The default hpd low level count threshold value is 100ms.
This means that the hpd being pulled down must last for 100ms
then hpd interrupt is triggered. This can cause the hpd
status to be misjudged in some scenarios.

Change-Id: I1999b0dd37e5f1dae2c2f35c7a84dd07efc77f03
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2024-09-11 17:12:04 +08:00
Damon Ding
01bd3d2b6a ARM: dts: rockchip: rk3506g-evb1: modify the mcu timing according to SI report
According to the SI report, the new mcu timing can meet
the signal needs for panel k350c4516t.

Change-Id: Ie6b72cdc97a676795dcb7ed44f93826e0d37dadc
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
2024-09-11 17:10:42 +08:00
Damon Ding
16c29be105 ARM: dts: rockchip: rk3506g-evb1: add read cmds and bypass timing for mcu display board
Read Read ID4(D3h) from panel K350C4516T for debug in
initialization process.

Change-Id: Ia5ecd6b22074ede496b898c8ad5dbcbafb6e7601
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
2024-09-11 17:10:42 +08:00
XiaoDong Huang
247f5deabf soc: rockchip: pm_config: replace memset with memset_io
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ia75fbfba4efd9d10eb2d15f5ae646135d858e0a0
2024-09-11 16:53:41 +08:00
Lin Jinhan
629aef9788 crypto: rockchip: set CRYPTO_ALG_INTERNAL for cra_flags
Rockchip's crypto driver is set to the CRYPTO_ALG_INTERNAL flag,
 which prevents it from being called by other modules of the system
 and is only used for librkcrypto use.

Fixed the panic bug caused by calling hmac(sha256) in Android CTS test:

[  234.124644][    C0] ------------[ cut here ]------------
[  234.124694][    C0] kernel BUG at arch/arm64/kernel/fpsimd.c:1832!
[  234.124708][    C0] Internal error: Oops - BUG: 00000000f2000800 [#1] PREEMPT SMP
[  234.165910][    C0] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G           OE      6.1.78-android14-11-g55b024554aae-ab11965736 #1
[  234.166912][    C0] Hardware name: Rockchip RK3576 EVB1 V10 Board (DT)
[  234.167486][    C0] pstate: 404000c5 (nZcv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[  234.168160][    C0] pc : kernel_neon_begin+0xe8/0x14c
[  234.168623][    C0] lr : cbc_decrypt+0x94/0x104
[  234.169037][    C0] sp : ffffffc008003ce0
[  234.169393][    C0] x29: ffffffc008003ce0 x28: ffffffc009faed80 x27: 00000000000000e0
[  234.170093][    C0] x26: ffffffc00a13e000 x25: 0000000000000001 x24: ffffff800dd85dc0
[  234.170792][    C0] x23: ffffff80f17e5540 x22: ffffff80f17e5600 x21: 0000000000000002
[  234.171492][    C0] x20: ffffff80c3720d70 x19: ffffffc009faed80 x18: ffffffc008005060
[  234.172192][    C0] x17: 000000000000003c x16: 000000000000003c x15: 000000000000003c
[  234.172891][    C0] x14: 0000000000000000 x13: fffffffe030dc9c0 x12: 000000000000003c
[  234.173590][    C0] x11: 000000000000003c x10: 0000000000000008 x9 : 0000000000000080
[  234.174289][    C0] x8 : 00000000000000c0 x7 : 0000000000000000 x6 : 189055e08898eccd
[  234.174988][    C0] x5 : 000000000000003c x4 : 0000000000000fc4 x3 : 0000000000000020
[  234.175687][    C0] x2 : 0000000000000030 x1 : 0000000000000020 x0 : 0000000000000000
[  234.176387][    C0] Call trace:
[  234.176667][    C0]  kernel_neon_begin+0xe8/0x14c
[  234.177092][    C0]  cbc_decrypt+0x94/0x104
[  234.177472][    C0]  crypto_skcipher_decrypt+0x3c/0x54
[  234.177932][    C0]  crypto_authenc_decrypt_tail+0xd8/0xf4
[  234.178423][    C0]  authenc_verify_ahash_done+0x5c/0x6c
[  234.178902][    C0]  rk_ahash_crypto_complete+0x10c/0x204 [rk_crypto]
[  234.179522][    C0]  rk_complete_op+0x78/0x100 [rk_crypto]
[  234.180049][    C0]  rk_crypto_done_task_cb+0xc8/0x100 [rk_crypto]
[  234.180641][    C0]  tasklet_action_common+0x260/0x4bc
[  234.181100][    C0]  tasklet_action+0x24/0x34
[  234.181492][    C0]  __do_softirq+0x11c/0x418
[  234.181883][    C0]  ____do_softirq+0x10/0x20
[  234.182274][    C0]  call_on_irq_stack+0x3c/0x74
[  234.182687][    C0]  do_softirq_own_stack+0x1c/0x2c
[  234.183121][    C0]  __irq_exit_rcu+0x54/0xb4
[  234.183513][    C0]  irq_exit_rcu+0x10/0x1c
[  234.183893][    C0]  el1_interrupt+0xa4/0xd8
[  234.184276][    C0]  el1h_64_irq_handler+0x18/0x24
[  234.184710][    C0]  el1h_64_irq+0x68/0x6c
[  234.185079][    C0]  cpuidle_enter_state+0x1d0/0x5b4
[  234.185526][    C0]  cpuidle_enter+0x38/0x54
[  234.185905][    C0]  do_idle+0x1d4/0x294
[  234.186268][    C0]  cpu_startup_entry+0x34/0x3c
[  234.186682][    C0]  rest_init+0xe0/0xe4
[  234.187042][    C0]  arch_call_rest_init+0x10/0x14
[  234.187477][    C0]  start_kernel+0x384/0x478
[  234.187866][    C0]  __primary_switched+0xc8/0xd4
[  234.188295][    C0] Code: f85f8e5e d65f03c0 943f17c6 34fffcd5 (d4210000)
[  234.188891][    C0] ---[ end trace 0000000000000000 ]---
[  234.204980][    C0] Kernel panic - not syncing: Oops - BUG: Fatal exception in interrupt

Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I9bace812173c232f16fd8cb72466d37fae98a5b6
2024-09-11 16:08:44 +08:00
Xuhui Lin
ad889adf73 spi: rockchip: Increase transfer completion wait time
Increase the transfer completion wait time to 4 seconds.

Change-Id: I0bc56ac219f3b470b2184e3411ccdadfc9a7f5ac
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
2024-09-11 09:39:04 +08:00
Jianwei Fan
c3f682ec2b media: i2c: tc35874x: fix 5V event report
Change-Id: I61c9b15f662b9e132bcf54b06866df3d873be880
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
2024-09-10 19:54:17 +08:00