The cs inactive interrupt status is effective in both irq and dma
transmission processes.
Change-Id: I6581e8dd74f70aa1c69b888a4acae7c03351b4fd
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1. The layout of controller registers has changed, remove legacy config;
2. Using the default value for grf register;
3. sync to use rk3568 parameter for phy PLL, signal test pass
4. Add 24MHz refclk for rk3528 PCIe, Enable the counting clock of the
rterm detect by setting tx_trim[14] bit for rx detecting.
5. set SSC modulation frequency to 31.5KHz
Change-Id: I45742c416d452037e61b7a7b8765269931d56402
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
This patch set the linestate filter time to support wakeup for
rk3528. Different from other platforms, Both the otg port and
host port have linestate_filter_con register, so we need to set
them separately.
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: I4a78dccbdb73c48436876b72e106a2eb608ea99d
This patch add usb2 phy support for rk3528 and modified the
rk3568_vbus_detect_control as a universal interface due to
more and more platforms may use this interface in the future.
Usb2 phy also has one different design for rk3528. It doesn't
has commonon control bit, we found that there is a phy inner
debug register which can control the pll out. So we can use
this register to support phy pll control for rk3528.
Add usb2 phy tuning for rk3528:
1. Turn off differential receiver in suspend mode for
the otg and host port to save power consumption.
2. Choose the Tx fs/ls data as linestate from TX driver
for otg port which uses dwc3 controller to improve
fs/ls devices compatibility with long cable.
3. Enable both the otg and host ports phy irq to pmu
wakeup source.
4. Set HS eye-height to 400mV for rk3528
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: Ia4a861bccd6a37db4e1ba42cede66a6b07947b5d
The cs inactive logic can always be triggered when the controller
is working, so the interrupt may be triggered when processing the
dma transmission completion interrupt.
Change-Id: I529140e43125ff3a06da67604a17afb585aafd72
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
The SPI_SR->busy is invalid for SPI slave write with ip version
ROCKCHIP_SPI_VER2_TYPE2.
Change-Id: Ib5d04a1a7859d7d47e5162f1db58f110dda8bad4
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
There are many restrictions on the use of the foresee devices Program
Load Random Data (84H), for example it's not allow after a block erase.
Change-Id: I345757016aa9b4c70b6cd5cca54f49166bb9dd99
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
VOP will triggle DMC at the following condition:
wb_en && wb_dma_finish && (vp lineflag || vp post full)
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I2ec972d74f7c8eab0088fcd96dc394e0d554020e
For compatibility with gki, dw-hdmi use callback
function instead of direct call dw-hdmi-cec wake up function.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I06fb65eadead5e3395bbd69a4dd465c95c684494
If the hdmi is plug out during the kernel logo phase and
hwc is not initialized, the hpd event cannot be received,
hdmi will not be disabled. Even if the hdmi is plugged in,
it will not actually be reinitialized, resulting in no signal output.
In this status, kernel must set mode_changed flag to true that
disable/enable hdmi when hwc enable hdmi.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I6aa0e8d7c3126b329d591de82a8fb91ec3f67f70
Kernel 4.19 edid parse process does not add picture_aspect_ratio
for HDMI 1.4 4K modes. This does not match uboot next-dev, that
will cause kernel logo display error.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I1b81f9b9c30ed86e671e2aa8b4a3d498e07c9410
When the frequency before and after color switching is the
same, the resolution switching process is not performed.
Instead, go through the following process:
connector atomic check--->set avmute--->config hdmi controller
-->config vop-->connector atomic commit-->clear avmute.
This way the HDMI output will not be interrupted, the black
screen time will be shorter, and the user experience will be
better.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: If2d0d9d21c2c343cd8e2b5135b214bc1a6f6706c
In order to switch HDR/SDR output status without
enable/disable CRTC, VOP color config should be
done in atomic_flush.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ic8baee19e41ac7379699bbca21667be00e7e5934
In order to achieve seamless HDR switching, avmute
must be unmuted after VOP atomic flush. So we
introduce connector commit.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ibf11da67c4388f50d8fa34aa5b4902a45ef89f6f
Support system wake up if hpd pin gpio irq occur when hdmi plug in.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I5a3896e8b1b86bccbda6681db26ab4285e3eec72
If cec in standby status, cec wake up interrupt will be
triggered when specific cec message is received.
Then input power key event to wake up system.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I91b4482ab78f91e5e9df66fa8384e118b08f35a2
1.Add support rgb bt2020 color space output.
2.Set AVI YQ to limited range.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I0a7d1ecbf2ab002328c8e6bcb115753e17e4bbb9
RK3528 hdmi hpd 5v io is always being pulled down.
This workaround is set hpd 5v io to gpio function and
receive hpd signal from sink.
When hpd status is changed, gpio interrupt will trigger,
then set the hdmi_snk_det reg to change the hpd status of
the hdmi controller. Finally trigger the hpd interrupt
of the hdmi controller.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Iac5140a09d3dda172f0125a25dbc8b281c8e0fa5
Add compatible string for Rk3528 gmac, and constrain it to
be compatible with Synopsys dwmac 4.20a.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I63d79df0812b5d2a40664aadc1ae36e6b2f9534a
Add constants and callback functions for the dwmac on RK3528 Soc.
As can be seen, the base structure is the same. In addition, there
is an internal phy inside with Gmac0.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I8a69a1239ed3ae91bfe44c96287210da758f9cf9
Use a common interface to implement power up/dowm for FEPHY,
which we could reduce codes.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ia7b42862abb20ea7395d6dad021621c8e1ededb9
This patch enable SAI which act as I2S/PCM/TDM, and much more
flexible protocol.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ie1295825040ebbd9dd3848ed1c961f616e52a60f
This patch enable SAI which act as I2S/PCM/TDM, and much more
flexible protocol.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I14b5f0ba183dddfdb97cf3365057e08201487d7c
Set dma maxburst per FIFO waterlevel for better performance
on high bit-rate situation, such as 192k 8ch 32bit situation.
Change-Id: Ida94609185b97c31bbfbb02ed65961c90f3d30f3
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch allow driver to set lanes auto depends on
common-use format, such as I2S, DSP_A, DSP_B etc.
And allow user to select lanes manually as required,
such as TDM32 x 4
Change-Id: If6adb2bded38faa3462c52286602506f991cc0e5
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
