To make android platform iommu work well, we need a unified compatible
name to match the new iommu definition in dtsi
Change-Id: Ied581653e1261fd0a21577f4e9ce3b915af135cd
Signed-off-by: Simon <xxm@rock-chips.com>
The rk3288, rk3368 and rk3366 have the same physical dsi id 0x3133302A,
so do not need to get dsi host id.
Change-Id: I0de1e9b7c0250b37ffdc2c39155c5f16afb48956
Signed-off-by: xubilv <xbl@rock-chips.com>
Assign rates for aclk_bus and aclk_peri according to our original design.
Change-Id: Iab4961d485421151be5dbdacf6929800150ab342
Signed-off-by: Feng Xiao <xf@rock-chips.com>
add 1296MHz, 1104MHz and 216MHz to the cpuclk_rate_table list
Change-Id: I1ea7ee432b7c69b89cb3c11a74e67d9d6af1a5dd
Signed-off-by: Feng Xiao <xf@rock-chips.com>
For sheep board, we have decided to assign vop full for
use with HDMI. And we can also change it in the board
dts in the further.
Change-Id: Id966615c84cef50f0e8d849e3840434ba7f7b7ec
Signed-off-by: Feng Xiao <xf@rock-chips.com>
We will need a pll to support all kinds of clock rate requirement
for HDMI which may change the rate at run time.
In order not to affect other clocks, remove the npll from the
parent list of other clocks and only DCLK_VOP(FULL or LITE) can
select npll as parent. Also add the ability for DCLK_VOP to set
the rate of its parent (which is now forced to NPLL).
Change-Id: I1e13ef1c4f1b9728f9c173454d5056780c47a95e
Signed-off-by: Feng Xiao <xf@rock-chips.com>
We need to init some signal related stuff
to make sure the SI meet the requirement.
Change-Id: I829203fb9cd2e93aa6acaa5288667f600370d781
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Coreboot choose dtb by its compatible string.
Add "google,rk3399evb-rev*" accordingly.
Support more versions for rk3399evb in the future.
If we later find we need to introduce differences between versions,
it's easy to change things.
Change-Id: I049b4f113b1694577a1f0be68f6b635ae13653c0
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Bool type true is exactly BIT(0), so
bool enable = true;
enable &= BIT(2);
enable will be false, which isn't the result we expected in this case.
Change bool type to u32.
The other fix is checking the res in probe() to skip the irq resource.
Change-Id: I2947c9f1e15cb92f03096d26a44759c107bfacd1
Reported-by: Simon <xxm@rock-chips.com>
Suggested-by: Simon <xxm@rock-chips.com>
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
set hdmi phy clock as 148.5Mhz when dclk rate over this frequency
Change-Id: I416b2b98fe42fafc45491b66252f245aed0f1364
Signed-off-by: xuhuicong <xhc@rock-chips.com>
It may caused a dead lock if we flush the hpd work in bridge disable time.
The normal flow would like:
IN --> DRM IOCTL
1. Acquire crtc_ww_class_mutex (DRM IOCTL)
IN --> analogix_dp_bridge
2. Acquire hpd work lock (Flush hpd work)
3. HPD work already in idle, no need to run the work function.
OUT <-- analogix_dp_bridge
OUT <-- DRM IOCTL
The dead lock flow would like:
IN --> DRM IOCTL
1. Acquire crtc_ww_class_mutex (DRM IOCTL)
IN --> analogix_dp_bridge
2. Acquire hpd work lock (Flush hpd work)
IN --> analogix_dp_hotplug
IN --> drm_helper_hpd_irq_event
3. Acquire mode_config lock (This lock already have been acquired in previous step 1)
** Dead Lock Now **
It's wrong to flush the hpd work in bridge->disable time, I guess the
original code just want to ensure the delay work must be finish before
encoder disabled.
The flush work in bridge disable time is try to ensure the HPD event
won't be missed before display card disabled, actually we can take a
fast respond way(interrupt thread) to update DRM HPD event to fix the
delay update and possible dead lock.
(am from https://patchwork.kernel.org/patch/8313001/)
Change-Id: Id7b357de0f497ff8c9f259fe31dc28be34f17083
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Note: Gustavo Padovan try to remove the controller and phy
power on function in bind time at bellow commit:
drm/exynos: do not start enabling DP at bind() phase
But for now driver need to read edid message in .get_modes()
function, so controller must be inited in bind time, so we
need to add controller init back.
(am from https://patchwork.kernel.org/patch/8312921/)
Change-Id: I32abee21665a7e1470f2898b7fbc925108f9d768
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Note: Gustavo Padovan try to remove the controller and phy
power on function in bind time at bellow commit:
drm/exynos: do not start enabling DP at bind() phase
But for now the connector status don't hardcode to connected,
need to operate dp phy in .detect function, so we need to revert
parts if Gustavo Padovan's changes, add phy poweron
function in bind time.
(am from https://patchwork.kernel.org/patch/8312901/)
Change-Id: I0ed1be541210f85883477f1b2a88bd8d57e390d6
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
(am from https://patchwork.kernel.org/patch/8313081/)
Change-Id: If99d29936aafd996c98568d6e184aee6d9c8bc47
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
(am from https://patchwork.kernel.org/patch/8312881/)
Change-Id: Id1432af874eb0a6dec819d7b7e735c1040f4bf5c
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
(am from https://patchwork.kernel.org/patch/8312861/)
Change-Id: I422216f58a18f2c2fee187b4f19de7b9d0fcd05a
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
(am from https://patchwork.kernel.org/patch/8312841/)
Change-Id: If7a422554ac09cd3ed40eac8191369df532c58bf
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
(am from https://patchwork.kernel.org/patch/8615371/)
Change-Id: Ibe22447ab881b7421e999479cbdfd529d183f6b4
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
for Exynos DTS file for dp-controller.
Beside the backward compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
(am from https://patchwork.kernel.org/patch/8312821/)
Change-Id: I79adafdb4a086d4a357678282cc653a7e3432da9
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
(am from https://patchwork.kernel.org/patch/8312811/)
Change-Id: Ia1d47783b735868a4f56231660d8309cf9c75923
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.
(am from https://patchwork.kernel.org/patch/8312791/)
Change-Id: Ia7f37daf40fa2d0516d5c44737ad36b5822c6015
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.
Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}.
(am from https://patchwork.kernel.org/patch/8312771/)
Change-Id: I8cbf7146d70143bb5d30b3fa971e19f034c30e62
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
In the original split we kept the register constants intact to keep the
diff small. Still the constants are Analogix-specific, so rename them now.
(am from https://patchwork.kernel.org/patch/8312781/)
Change-Id: I714d60bc941b7a992dd34d4c0804576bd07ca84d
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
