This driver use runtime PM autosuspend mechanism to manager clk.
pm_runtime_use_autosuspend(&adev->dev);
pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
So, after ref count reached to zero, it will enter suspend
after the delay time elapsed.
The unbalanced PM:
* May cause dmac the next start failed.
* May cause dmac read unexpected state.
* May cause dmac stall if power down happen at the middle of the transfer.
e.g. may lose ack from AXI bus and stall.
Considering the following situation:
DMA TERMINATE TASKLET ROUTINE
| |
| issue_pending
| |
| pch->active = true
| pm_runtime_get
pm_runtime_put(if active) |
pch->active = false |
| work_list empty
| |
| pm_runtime_put(force)
| |
At this point, it's unbalanced(1 get / 2 put).
After this patch:
DMA TERMINATE TASKLET ROUTINE
| |
| issue_pending
| |
| pch->active = true
| pm_runtime_get
pm_runtime_put(if active) |
pch->active = false |
| work_list empty
| |
| pm_runtime_put(if active)
| |
Now, it's balanced(1 get / 1 put).
Fixes:
commit 5c9e6c2b2b ("dmaengine: pl330: Fix runtime PM support for terminated transfers")
commit ae43b32891 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power Management support v12")
Change-Id: Ib1feb508c16afb4bc9ced0c3660f2b6b4a19c068
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
The RV1106 EVB2 board is designed for some products that's required
thunder-boot feature, and use spi-nor flash as default.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: Ie0543368c9536d820995313eca4f12529aa4d391
In preparation for adding new driver to support starting
decompress ramdisk.
And make the hclk_mmc is available before accessing the registers.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: Icbd51f2798367430443bae9af5656891b93ac3bd
For some MTK solution routers, there may be link up/down situation,
after disable these two function, the problem can be solved, and the
power consumption is tested, and there is no increase.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I46122188b2fcb67dc02630827b4b631ecfc0ec5e
SRAM accessed by PKA requires word alignment.
It will crash if optimized to memset/memcpy.
Change-Id: I0122ff7ffab3835c513c39d57aa5441655cd2b03
Signed-off-by: Wang Xiaobin <xb.wang@rock-chips.com>
Set rx default size to 16, if not enough, please change board dts.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Iab1812d1eb9b7156b58b39d8199d0b55ae329bd0
Enable HPD interrupt after the device is powered on.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I6f95c30e4af7fd13b3dc6843cd5fc7c7babdf29f
dw_pcie_write_dbi2() is not export.
irq_set_affinity() is not export before v5.14.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I780ed626c1b99f1bd7af7798582a62235003fbf6
Compared with rx refill, the buffer at initialization level also needs
to do this action to avoid being flushed into wrong data after rx received
data.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Icad68f5e22c4dc3dc5ee007b2bc0d3120ceefbc9
256 LLI were pre-allocated for multiple scatter lists
to complete in one calculation.If sg nents exceeds
256 in a single calculation, the calculation is
divided into multiple calculations.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I39282efc5a2743e12bd33daa94c89a2ed83fb400
Unify the process regardless of whether the data comes from DMA buffer.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I140f0e03b39c8d7b37af2cc76e3aa314f29a73c7
If FIQ_GLUE is enable, uart interrupt is group0, but all
other interrupts are group1. AIAR is for group1, IAR is
for group0 and group1. We need IRQ handles group1 interrupts
only, FIQ handles group0 interrupts.
Fixes: 4c9f0407c6 ("irq-gic: support fiq")
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: I062e6cafcd8728165b6eda8b82f92f7a90672132
Make the downstream mux work fine，fix reboot and suspend issues.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I06e6f6c22238da6aec0a8690564743dff02db0ad
The sdio requires the cmd and data pins to pull up by soc.
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: I7390dad3e1af19c5cae778064e49e47eb8514baf
For rk3588, the input/output of the clock direction needs to set
the php_grf register, and the pclk of php_grf is associated with
pclk_gmac, so you need to set the input/output before closing
pclk_gmac.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Idddec040660aaadd80d7dd6d8aba6220b65425fe
The single-pmic configuration is based on the EVB7
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: If3e9136ce9e0ebbd50780bc7d06481e6c69bcf12
This reverts commit 6fbbbac945.
Which make eMMC boot failed.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I7ed10941a1031d752a0a7567f60fd42304a33d03
When reset the dp controller, if a DP device is connected, the dp
controller will generate a hotplug irq, which is a unexpected hotplug
event.
To filter this hotplug event, disable irq before reset the DP
controller. After dp controller reset, wait the first hotpulg event
then clearing the hotplug interrupt status bit and enable dp
controller irq.
Fixed:
commit f14693316b ("drm/rockchip: dw-dp: reset dp controller status")
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ic4cabd3b816121b2d1109a5bbfe608f615971953
