This patch add property 'rockchip,no-dmaengine' to
support register DAI without PCM, and it's usually
used for Multi-DAIs which combine DAIs into a union one.
Change-Id: I4e0da8fae2c692601e05118442218de0f7b4efee
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch add support for keeping BCLK / FSYNC always on.
it's required by some devices, such as HDMI, PA, etc.
For example: on HDMI situation
There are some TVs require maintaining N/CTS packets or AUDS
packets to keep audio logic active, otherwise, the first tone
may be lost.
In order to optimize the user experience, we need to ensure
continuous transmission of N/CTS and AUDS packets from the
HDMI-TX, so that the SINK TV devices can maintain audio logic
activation, promptly process audio data, and achieve the
completeness of the first tone.
We init a 48k I2S-STANDARD clock timing as default.
Change-Id: I298b0ad2d53bdc41927f567c2af481f2a0bd5422
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
There is a issue of stuck during dual-core collabration,
and the hw timeout count will be blocked by default,
and only soft timeout can be triggered to exit.
However, the soft timeout is too loog, so config reg to not mask the hw
timeout.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: If801b8ba3b463094ea497fae829f772de7ade382
In some platform, can not do pmu_idle_request before cru reset.
Resetting without pmu_idle_request while the hw is running
will result in a bus err.
So stop hw first before cru reset to prevent the issue.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I62ace147a0d72adb774fed989b34c7bf22af48ac
This patch add support for Clk-Auto Switch.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I2d3b10fcf4cc55ba005d1c9da1049190882f7494
* Support 8-bits width
* Support Mono channel
* Support up to 384k samplerate
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I9f1c10bad2bfb9a3beee1dd91508158e79da2492
Modify the micorvolt of vdd_arm to support the new hardware.
Signed-off-by: Zhichao Guo <zhichao.guo@rock-chips.com>
Change-Id: Id4e102c0a72898c27e0f2547e08c5d5095edfb76
If no need to activate the decompress flow, using CONFIG_ROCKCHIP_THUNDER_BOOT_MMC
should be better.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ic9750ab71cc0d7c5beddd41f11ab71aa4df69bff
dsi->connector.funcs may be NULL, because drm connector may be
implemented in drm bridge which attached dsi.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Id8668a70405ff41d770784cb9a5db3b16d92f3a3
Including:
kbase_device_kinstr_prfcnt_init(),
kbase_device_kinstr_prfcnt_term(),
kbase_device_io_history_init(),
kbase_device_io_history_term.
To resolve compilation errors when CONFIG_DEBUG_FS is not enabled.
Change-Id: Ibeaf97bd9fdbbb45308160e11c4dbb386a0dea71
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
1. get the value of pvtpll@0.9v from otp.
1. adjust opp-table by pvtpll value.
2. adjust opp-table by mbist-vmin.
3. adjust opp-table when low temperature.
Change-Id: Idc0c0e811c80d1b9b51d4a4f5c7176c546558386
Signed-off-by: Liang Chen <cl@rock-chips.com>
An interrupt may be triggered first,
but hdmi->i2c is not registered yet.
Change-Id: I45b0adc71ccdd6bf7543601b587976fa47ffd7d4
Signed-off-by: Chen Shunqing <csq@rock-chips.com>
This is a PCIe function driver for rockchip RKEP demo which works on RC
side, it includes following features:
1. Support rc dma
2. Support mmap reserved memory
3. Add dma msi obj irq signal
4. Add user msi obj irq signal
5. Support RKEP-boot
Change-Id: Id71ebd31f86b688d3e6e07ce5055aad81ce7e206
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
When the hdmi is plugged in and out after uboot but
before kernel initialization, the TV will enter hdmi 1.4 mode,
hdmi 2.0 resolution can't be display.
In this case, we need to disable/enable hdmi again to make TV
into hdmi 2.0 mode again.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I39fbe519d54329ae7db57904013bfdef6f5a068e
HWC will set hdmi out of hdr mode then disable hdmi
when hdmi plug out in hdr mode.
If hdmi is disconnect edid is null, mode valid check
is always failed, HWC set hdr disable will failed.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I12ebf23539be17b338617131e879296ed20d6a95
1.Add phy configuration retry when signal can not be locked.
2.Add the judgment that signal locking has stabilized.
3.Add the judgment of signal loss when starting stream.
4.Modify the calculation method of pixclk and fps in YUV420 format.
5.When DMA is enabled, if the 5V_Det level changes, an interrupt will be
forcibly triggered to reset the controller in BL31 as soon as possible.
Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
Change-Id: I27846bca7059d834b5bd069b5959a2279295568d
