VOP has a limitation of act_width on rk3568:
(1) The act_width should align as 4 pixel at afbc mode
(2) can't handle a act_width % 16 = 1
VOP on rk3588 has no such limitation.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I56f2ff32ac384bff81b6b911cd10ef599e5f44c3
We should set both VP->DUAL_CHANNEL_CTRL.dual_channel_en
and DSP_INTERFACE_EN.mipi_dual_channel_en when drive
a dual channel mipi dsi on rk3588, this is different
from rk356x.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I784f9556903126bae52b3063eb23fbf0a0193739
1. Set earlycon base address 0xfeb50000
2. Set fiq_debugger interrupts id 423
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: Ia875782dd417b3d2202794293eb76bf0b59e5b13
1. Set earlycon base address 0xfeb50000
2. Set fiq_debugger interrupts id 423
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: I4069d5ec5e6633c903a5e84f099c982d87c4ca36
When cluster work at two win mode:
act_w + xoffset % 16 <= 2048
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I1326b02ede58b9a96960ad0d262cb1665bd29525
Some clk invert(dclk invert) control in SYS_GRF
Some interface enable(hdmi/edp enable) control in VOP_GRF
hdmi_vsync/hsync_pol control in VO1_GRF
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Ia3972c9d207c9385b4512c96ea8e2d66e8fa03d5
This reverts commit debf378724.
The patch a82c7abdf8 ("usb: dwc2: hcd: Fix host channel halt flow")
can fix the issue.
Change-Id: I9a014c42cf942cab22480b5faab13c802e7fd47e
Signed-off-by: William Wu <william.wu@rock-chips.com>
The parameters g_dma and g_dma_desc is used for gadget,
so let's use host_dma and dma_desc_enable instead of them.
And it needs to update the chan->halt_status for non-split
periodic channels rather than return immediately, otherwise,
the software will not release the channel when the channel
halt interrupt is triggered next time.
In addition, it only needs to wait for the core generates
a channel halted if halt_status is DWC2_HC_XFER_URB_DEQUEUE.
Fixes: a82c7abdf8 ("usb: dwc2: hcd: Fix host channel halt flow")
Change-Id: I455444af020ff751406295f21133ff6a950c04dd
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
Fixes: d58bcc8c2b ("soc: rockchip_system_monitor: Add support to limit volt during system startup")
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I3ca0aa2b6563c5be9fddd9fee04145ce8e15c32c
Put the clock configuration of GMAC into the gmac driver and implement
corresponding functions.
Fixes: 2627dcd2c9e9("net: ethernet: stmmac: dwmac-rk: Add gmac support for rk3588")
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: If9bd639db31f44602af56dc20b81688ba67702c2
HDMI/eDP/DP on RK3588 also support dual channel mode
like mipi dsi.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I06454d3c64bc6a283d180c57fac6e8464ff6ca19
1.It's to follow the concrete spi develop guild instead of these
rough introduction.
2.Remove useless filesystem operation
Change-Id: I0c0904720cd01bc1383f4722e9febf152e7c89e0
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
RK3588s evb supports pcie;
evb2 does not have pcie.
Note that the pin name in schematic is named by PHY;
and here is the map for phy and controller on rk3588s:
pcie2x1l0 - Not exist in rk3588s
pcie2x1l1 - PCIE20_2(PHY MUX_2)
pcie2x1l2 - PCIE20_0(PHY MUX_0)
Change-Id: Ibf4a66f79c377155d1c23d5f99a63306f9556432
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
On RK3588 platform, there are two voltage inputs for each cluster,
VDD_LOGIC and VDD_MEM are supplied by two regulators. when scaling
voltage inputs of the cluster, the voltages of two regulator inputs
need to be controlled by software under the SoC specific limitation:
VDD_MEM: 675mV ~ 950mV
VDD_LOGIC: 550mV ~ 950mV
VDD_MEM - VDD_LOGIC <= 400mV
VDD_LOGIC - VDD_MEM <= 150mV
So when scaling up voltage, change the voltage of VDD_MEM before
VDD_LOGIC, and when scaling down voltage, change the voltage of
VDD_LOGIC before VDD_MEM.
Change-Id: I1a603335e0fd98b1b70e4d0ccbcad10d33cc8a8a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
