It is needed to enable both dclk_bypass and data_bypass
in mcu mode.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I019a2242a6566fa5cfad0d9b981f020dc755c241
Add the clock tree definition for the new RK3506 SoC.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ib5e47bd03620cb7540fa827e29425c243f633a82
Add the dt-bindings header for the rk3506, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3506.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Id92261ad2a6cd68d192f2159f0f7f5edffa60a2d
Document the device tree bindings of the rockchip rk3506 SoC
clock and reset unit.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: If8c0e19fab9687d488ffce1607b8555f3e7cda35
When setting an RTC alarm, the S35390A_CMD_STATUS2 register will be
set again, which unintentionally disables the 32KHz output, this commit
adds the necessary configuration to set the S35390A_INT2_MODE_32K,
ensuring that the 32KHz output remains enabled at all times.
as a result of this change, the previous commit
7f151d9170 is no longer necessary.
Signed-off-by: Xu Xuehui <xxh@rock-chips.com>
Change-Id: I8607899676bd624e00032eeca1a21a0658f3b71a
For force-hpd, It should be regard as always connected, so
it don't read the register to get the connect status.
Change-Id: I7082bb1ae56a640a43a800b9a934da7700e76de5
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
This is a merge error at following commit:
commit 32062f68cc ("drm/rockchip: vop2: update dsc pd status when show logo with dsc")
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I603abd28fb9e1ccdbb06fa1e25c3a64b35b8d293
Read default register value and backup to regsbak must after pd power on, so we
can get correctly value, but the pd power on action depend on regsbak, so
we add extra regsbak for power_ctrl.
Fixes: 6282856b67 ("drm/rockchip: vop2: move power up plane pd before read regsbak")
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I465b0ec76d4e1233c40e79528ee42b5c5c2fb727
According to the SI report, modify pe/vs configs of new
link rate R216/R243/R324/R432, which are configured to
nearby RBR/HBR/HBR2 configs in the past.
In addition, modify the pll configs to pass SSC test.
Change-Id: Ic10ea8289f47cfc93bd2c08231b76c68a6e4b4d2
Signed-off-by: damon.ding <damon.ding@rock-chips.com>
note: gc05a2 flip & mirror use the same register;
but write value to the register not valid immediately,
so need record it in variable, to avoid being covered.
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: Ice9c9fcefdbf9fa56a83f9b049e434cfe1c23bba
The counter result read after disabled may be inaccurate,
because the arbitration has been removed.
Change-Id: Id91069721ef5767d81bb8bced0ae429840711ad4
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
According to IC design, it is not recommended to enable/disable
pclk in counter mode, because the pclk is used to sync counter
result.
Change-Id: Ibb44082ae1091d38a51f0d1f0c1879769109bc86
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
According to the datasheet, CLK_RATIO_2X should be enabled
for interlace modes otherwise the 720x480i60/720x576i60
modes may be mistaken for 360x480p60/360x576p60.
Change-Id: I7efa084b7d3a05bdafd0dc17264784db178d05c6
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Clear output_if of rockchip_crtc_state in rockchip_rgb_encoder_disable()
only if active_changed flag of drm_crtc_state is true,
otherwise the output_if related checks may be affected
in .atomic_enable() of crtc.
Change-Id: Id15873feebd420a77c8949ea6601b9f33c18188c
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The logs about max clock check may be too frequent, so
replace DRM_DEV_ERROR() with DRM_DEBUG_DRIVER().
Change-Id: Ia5e4ad4a7dc00863e99d9b6cb92f3a812c1171e9
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Some GigaDevice ecc_get_status functions use on-stack buffer for
spi_mem_op causes spi_mem_check_op failing, fix the issue by using
spinand scratchbuf.
Fixes: c40c7a990a ("mtd: spinand: Add support for GigaDevice GD5F1GQ4UExxG")
Change-Id: I061911754ab4a3d69bfa2ebbb17af8f14027e5cc
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20231108150701.593912-1-han.xu@nxp.com
(cherry picked from commit 59950610c0c00c7a06d8a75d2ee5d73dba4274cf)
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
when the kernel suspend abort with is_hall_wakeup true,
mh248 resume will use wrong state of is_hall_wakeup
to send powerkey event to wakeup screen.
Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
Change-Id: Ifc8d83f49329631e9088fee9111b295c77e05a8a
The SDI1/2/3 and SDO1/2/3 for SAI1 on RK3576 is iomux functions.
Change-Id: I2292e4c3b5c75044e343d19c3557724591365836
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
in non-HDR mode, short gain and long gian need to be set the same
values.
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
Change-Id: Idaa14c389a20b2518757303538dc19fb8154695d
