This patch implements a combo phy driver for Rockchip SoCs
with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
sata-phy or sgmii-phy.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I86726e7eee643ea4cb3fadc56b0ee729903afc4f
When PMIC irq occurs, regmap-irq.c will traverse all PMIC child
interrupts from low index 0 to high index, we give fall interrupt
high priority to be called earlier than rise, so that it can be
override by late rise event. This can helps to solve key release
glitch which make a wrongly fall event immediately after rise.
Change-Id: Ieda1d6fd3c50cc36742a4740504ec7ce12ea509b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
RKPM_DBG_FSM_SOUT enables PMU FSM state signal output through
GPIO4_D5/SDMMC_CLK during sleep, mainly for debug PMU FSM flow.
Some one may use this pin as LED light, it's fine to drop it
to avoid influence on LED.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I54705292226d82829bc37db0758aa0d9a9995658
RKPM_DBG_FSM_SOUT enables PMU FSM state signal output through
GPIO4_D5/SDMMC_CLK during sleep, mainly for debug PMU FSM flow.
Some one may use this pin as LED light, it's fine to drop it
to avoid influence on LED.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I82af5fa676d6db8b81e877729c44b976bbfa9ea5
The vdd_logic is a pwm regulator. Since '#pwm-cells = <2>', there
is not polarity invert support by pwm driver, so we have to add
property 'pwm-dutycycle-range = <100 0>' to support polarity invert
by pwm regulator driver itself.
Change-Id: Ie5d2cda67ce19dc792f96263836bab658d385681
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
In memmap_init_zone, it check all pages valid or deferred by single page,
then zero and init the corresponding page struct. It is safe to zero all
page struct in advance at once no matter what the state of every page is.
This can save time when booting kernel.
Change-Id: Ieb5864231fbc751e9438be488a77ce442b91ce7b
Signed-off-by: Simon Xue <xxm@rock-chips.com>
The Seagate Expansion Portable Drive HDD (idVendor=0bc2, idProduct=2321) is reported to fail to work on rockchip platforms
with the following error message when do read/write operation by dd command:
xhci-hcd xhci-hcd.11.auto: Ring expansion failed
According to tkaiser's suggestion[1], we can try to increase the kernel's
coherent-pool memory size to fix this issue. The kernel coherent-pool memory
size was limited at 256KB by default. When set the DEFAULT_DMA_COHERENT_POOL_SIZE
to 1MB, the error "Ring expansion failed" can be fixed, but it still not
work with the other error message:
xhci-hcd xhci-hcd.12.auto: ERROR Unknown event condition 34 for slot 1 ep 3 , HC probably busted
sd 0:0:0:0: [sda] tag#16 uas_eh_abort_handler 0 uas-tag 17 inflight: CMD OUT
...
scsi host0: uas_eh_bus_reset_handler start
xhci-hcd xhci-hcd.12.auto: ERROR Transfer event for disabled endpoint slot 1 ep 6 or incorrect stream ring
Falling back to USB mass storage can solve this problem, so ignore UAS
function of this HDD.
[1] https://forum.armbian.com/topic/4811-uas-mainline-kernel-coherent-pool-memory-size/
Change-Id: I0d817cc3aaea548c2060b323c3077c6cbbd3bb6e
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
When test more than three Genesys Logic usb3 storages
(VID : PID = 0x05e3 : 0x0749) on rockchip platforms with
usb3 host port (e.g. rk3328/rk3399) at the same time,
test commands like this:
for dev in `ls /dev/sd?1 | sed -e 's,1$,,'`; do
echo dd if=$dev of=/dev/null
dd if=$dev of=/dev/null &
sleep 1
done
The test fail with the following error log:
xhci-hcd xhci-hcd.9.auto: xHCI host not responding to stop endpoint command.
xhci-hcd xhci-hcd.9.auto: Assuming host is dying, halting host.
xhci-hcd xhci-hcd.9.auto: Host not halted after 16000 microseconds.
xhci-hcd xhci-hcd.9.auto: Non-responsive xHCI host is not halting.
xhci-hcd xhci-hcd.9.auto: Completing active URBs anyway.
xhci-hcd xhci-hcd.9.auto: HC died; cleaning up
This patch sets the max_sectors to 128 (64K) to workaround
this issue, and it doesn't affect the transmission rate.
Change-Id: Idd9cc81659d27c12b142f6c4375558c2262e800d
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
These two devices give the following error on detection.
Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
xhci-hcd xhci-hcd.5.auto: ERROR Transfer event for disabled endpoint
or incorrect stream ring
The same error is not seen when it is added to unusual_device
list with US_FL_NO_REPORT_OPCODES and US_FL_BROKEN_FUA passed.
Change-Id: Ia1035ea597c65ad7112f68f5cbdd792875ee2995
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
If the parent of uvc device has a quirk for broken
auto-suspend function (e.g. rk3328 usb 3.0 root hub),
we also need to disable auto-suspend for the uvc device.
Change-Id: Ida8d05a411f49f39e13cad3ec837a56598b4a630
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
We found that some Sonix usb cameras(e.g. idVendor=0c45,
idProduct=64ab or idProduct=64ac) can't support auto-suspend
well on rockchip platforms(e.g. rk3399).With auto-suspend,
these usb cameras MJPEG will display abnormally on all usb
controllers(DWC2/DWC3/EHCI). So we need to disable auto-
suspend for these special usb cameras.
Change-Id: I08c87cf5c9fa5ebe076b5dd3e873b74c5ec2cb83
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The commit 62b2a34a21 ("uvcvideo: add quirk for devices
with broken auto suspend") introduced quirk to workaround
an issue with some HD Cameras.
There is one more model that has the same issue - idProduct
=0x9320, so applying the same quirk as well.
Change-Id: I24e3fc1746a9d21d529bc91f52fd5822e998bd93
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
We found that some usb cameras(e.g. Manufacturer: HD Camera
Manufacturer, idVendor=05a3, idProduct=9230) can't support
auto-suspend well on rockchip platforms. With auto-suspend,
these usb cameras MJPEG will display abnormally on all usb
controllers(DWC2/DWC3/EHCI). So we need to disable auto
suspend for these special usb cameras.
Change-Id: Ibf50ed77edff0012a112dc42f09e022055908829
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Some USB host controller seems to have problems with
autosuspend. For example, Rockchip rk3328 SoC USB 3.0
wouldn't handle remote wakeup correctly with external
hub after entered autosuspend, caused to resume SS
port fail.
This patch introduces a new quirk flag for hub that
should remain disabled for autosuspend.
Change-Id: I6d14222b2c5025583fea811a6afd6abd22f41cb9
Signed-off-by: William Wu <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch adds superspeed descriptors in device
applications to support USB 3.0 ffs gadget.
Change-Id: I5a364c935b1d30e2e929791ff16a34cf0d1c87e1
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The spi which's version is higher than ver 2 will automatically
enable this feature.
If the length of master transmission is uncertain, the RK spi slave
is better to automatically stop after cs inactive instead of waiting
for xfer_completion forever.
Change-Id: If99e51d35391b824f48e31a3e4508db036593c8a
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1.Add standard spi-cs-high support
2.Refer to spi-controller.yaml for details
Change-Id: I899bce8d9418ee99c784726bb56534aaed27c00b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1.Add standard cs-gpio support
2.Refer to spi-controller.yaml for details
Change-Id: I8f839189038afd77d534d767d938c845aa54fedb
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Add compatible string for rv1126 for potential applications.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Change-Id: I2ad2de0c715b064870b35214f25e9705412fd62f
Fixes: f27d8c9975 ("spi: rockchip: get pinctrl for lookup pinctrl state")
Fixes: 87dbea63d5 ("spi: rockchip: set higher io driver when sclk higher than 24MHz")
Change-Id: I963c92eab7f7bff0b32e2ac262aa79f0667f39ee
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
RK3568 u2phy used shared interrupt and do not used id irq.
Change-Id: I341cc0edb0f74996f159c095545465673cc2a990
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Test on RK3568S EVB1, the otg device data eye test fail with
far end template when use 1.2 meter long cable. So tuning
the hs eye height from 400mv(default) to 437.5mv. And we
test on RK3568 EVB1, it can also benefit from this patch.
Change-Id: Ie2342aba5546990838fdd6faf27a007a8843fd0d
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
When do USB 3.0 Receiver Jitter Tolerance Test, it fails at
Sj Frequency 2.0/4.9/10.0 [MHz]. This patch adjusts the PLL
parameters for USB to pass the Receiver Jitter Tolerance Test,
and it's helpful to improve the USB 3.0 signal compatibility.
Change-Id: I58eb687a4677fe22cf5bc324578b033526310859
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
If the Type-C PHY works as DP 4 lanes, the Tx/Rx lanes
of Type-C USB 3.0 PHY is used for DP lanes, so it needs
to force the USB 3.0 to USB 2.0 only, and make sure USB
3.0 xHCI controller doesn't support USB 3.0 port.
With this patch, an ASUS Type-C to HDMI dongle which
supports DP 4 lanes and USB 2.0 simultaneously can
suspend/resume successfully.
Change-Id: I77049702c768bd56d638d11c29aae07eeb608282
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Bind / unbind stress testing of the USB controller on rk3399 found
that we'd often end up with lots of failures that looked like this:
phy phy-ff800000.phy.9: phy poweron failed --> -110
dwc3 fe900000.dwc3: failed to initialize core
dwc3: probe of fe900000.dwc3 failed with error -110
Those errors were sometimes seen at bootup too, in which case USB
peripherals wouldn't work until unplugged and re-plugged in.
I spent some time trying to figure out why the PHY was failing to
power on but I wasn't able to. Possibly this has to do with the fact
that the PHY docs say that the USB controller "needs to be held in
reset to hold pipe power state in P2 before initializing the Type C
PHY" but that doesn't appear to be easy to do with the dwc3 driver
today. Messing around with the ordering of the reset vs. the PHY
initialization in the dwc3 driver didn't seem to fix things.
I did, however, find that if I simply retry the power on it seems to
have a good chance of working. So let's add some retries. I ran a
pretty tight bind/unbind loop overnight. When I did so, I found that
I need to retry between 1% and 2% of the time. Overnight I found only
a small handful of times where I needed 2 retries. I never found a
case where I needed 3 retries.
I'm completely aware of the fact that this is quite an ugly hack and I
wish I didn't have to resort to it, but I have no other real idea how
to make this hardware reliable. If Rockchip in the future can come up
with a solution we can always revert this hack. Until then, let's at
least have something that works.
This patch is tested atop Enric's latest dwc3 patch series ending at:
https://patchwork.kernel.org/patch/10095527/
...but it could be applied independently of that series without any
bad effects.
For some more details on this bug, you can refer to:
https://bugs.chromium.org/p/chromium/issues/detail?id=783464
Change-Id: I7909731247739694f56bf89ab3064889f2b34d3c
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(am from https://patchwork.kernel.org/patch/10105833/)
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Change-Id: I195727b2a81130606e66ffc4471df74e5782a7fa
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
I test on RK3399 IND EVB running Android R system, and
set the USB gadget as UVC function via configfs, both
the USB 2.0 and 3.0 UVC have preview abnormal problems.
If the CPU enter deeper sleep, the USB DMA transfer gets
corrupted, and the UVC ISOC transmission lost data.
This patch puts in a "pm_qos_latency" requirement which
will keep the CPU out of the deeper sleep states when
UVC stream on. And allow the CPU to enter deeper sleep
state after UVC stream off.
Change-Id: I808290f124c6a32da3888819348093a205bfad61
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch adds uvc_function_suspend and uvc_function_resume
for uvc function. With this patch, if usb bus enter suspend
or resume state, the usb controller driver will call the
uvc_function_suspend or uvc_function_resume to send event
to uvc app.
Change-Id: I9c584aae25298747c5a287243cb3efd71c8adfe6
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch add new uvc trace for setup request processing.
1. enable trace
echo 4 > /sys/module/usb_f_uvc/parameters/trace
2. dump trace
dmesg
Test on RV1109 EVB with UVC function when streaming on:
[ 426.441316] uvcvideo: setup request a1 81 value 0100 index 0003 001a
[ 426.450280] uvcvideo: uvc_send_response: req len 26
[ 426.450444] uvcvideo: event_setup_out 0, data len 26
[ 426.451545] uvcvideo: setup request 21 01 value 0100 index 0003 001a
[ 426.460862] uvcvideo: uvc_send_response: req len 26
[ 426.461014] uvcvideo: event_setup_out 1, data len 26
[ 426.461173] uvcvideo: setup request a1 81 value 0100 index 0003 001a
[ 426.485791] uvcvideo: uvc_send_response: req len 26
[ 426.486672] uvcvideo: event_setup_out 0, data len 26
[ 426.487145] uvcvideo: setup request a1 83 value 0100 index 0003 001a
[ 426.496529] uvcvideo: uvc_send_response: req len 26
[ 426.496655] uvcvideo: event_setup_out 0, data len 26
[ 426.497485] uvcvideo: setup request a1 82 value 0100 index 0003 001a
[ 426.506737] uvcvideo: uvc_send_response: req len 26
[ 426.507195] uvcvideo: event_setup_out 0, data len 26
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: If882728e891d033c249e6c466b40d3e2a28bccb6
According to USB Audio Device 1.0 Spec, Ch4.6.1.1:
The wMaxPacketSize of endpoint is defined as follows:
Maximum packet size of endpoint is capable of sending
or receiving when this configuration is selected. This
is determined by the audio bandwidth constraints of
the endpoint.
In current code, the wMaxPacketSize is limited to 200,
and the bInterval is set to 4 (1ms). That is, the maximum
bandwidth over USB bus is 200 * 1000 = 200000 bytes.
We find an issue about bandwidth limitation when we try to
support UAC1 with 8ch * 16bit * 16KHz on RK3308 platform,
which needs more bandwidth than it can support.
This patch sets the wMaxPacketSize dynamically according
to the parameters of UAC1. It is similar to the same thing
done earlier for f_uac2.
Change-Id: I9af3fd7665a80b5eb0cfb5dc91ebe2c20df1dd46
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch add uevent to notify the application layer how much ppm
is different between USB clk and AUDIO clk.
The event include two parts USB_STATE and PPM. For example:
g_audio_work: sent uac uevent USB_STATE=SET_AUDIO_CLK PPM=12
g_audio_work: sent uac uevent USB_STATE=SET_AUDIO_CLK PPM=-1
Note: The ppm compensation depends on the method implement of
clk drift and compensation in the rockchip_pdm.c driver. So if
you want the ppm compensation to take effect, please make sure
the commit "ASoC: rockchip: pdm: Add support for clk compensation"
is merged.
Change-Id: Id25411397fe376342c773c11f1989ed5854f8ad9
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
