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Author SHA1 Message Date
Wyon Bi
40a5f5d476 phy/rockchip: Add driver for Rockchip Naneng eDP Transmitter PHY 
DPTPHYT22ULP is designed for chips that perform eDP/DP data
communication while operating at low power consumption.
The main link is a multi-gigabit transmitter macro which
enable speed up to 4.0Gbps data transmitter with optimized
power and die size, also it can be easily fabricated and
implemented in a video system. The AUX channel is a halfduplex,
bidirectional channel consisting of one differential pair,
supporting the bit rate of about 1Mbps.

Macro consists of multi-main link transmitter channels,
AUX channel, one PLL and bias-gen unit. The main link
transmitter performs dedicated P2S, clock generator,
driver with preemphasis and self-test. Each of the channels
can be turned off individually.

Change-Id: Idf58991ff1bdd4557c4cfadf2dc047e95eca7668
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2020-11-10 14:17:57 +08:00
Jianqun Xu
34473954c3 power: rockchip-io-domain: fix rk3568 grf offset 
Change-Id: Ie3315fb6374ab0f6ad82caa137ab086c5f208c97
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2020-11-10 14:13:08 +08:00
Yuti Amonkar
c5771fc0a5 UPSTREAM: phy: Add DisplayPort configuration options 
Allow DisplayPort PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The configuration structure is used for reconfiguration of
DisplayPort PHYs during link training operation.

The parameters added here are the ones defined in the DisplayPort
spec v1.4 which include link rate, number of lanes, voltage swing
and pre-emphasis.

Add the DisplayPort phy mode to the generic phy_mode enum.

Change-Id: Id68cbd69c0938bd64402b8af7b6b37b168472848
Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry picked from commit 42d068472d)
 2020-11-10 12:53:05 +08:00
Maxime Ripard
2c1bae131a UPSTREAM: phy: Add MIPI D-PHY configuration options 
Now that we have some infrastructure for it, allow the MIPI D-PHY phy's to
be configured through the generic functions through a custom structure
added to the generic union.

The parameters added here are the ones defined in the MIPI D-PHY spec, plus
the number of lanes in use. The current set of parameters should cover all
the potential users.

Change-Id: Ie5a12064ba59a1a2c8628bd34c4c2b4996559ec3
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry picked from commit 2ed869990e)
 2020-11-10 12:53:05 +08:00
Maxime Ripard
01503fa839 UPSTREAM: phy: Add configuration interface 
The phy framework is only allowing to configure the power state of the PHY
using the init and power_on hooks, and their power_off and exit
counterparts.

While it works for most, simple, PHYs supported so far, some more advanced
PHYs need some configuration depending on runtime parameters. These PHYs
have been supported by a number of means already, often by using ad-hoc
drivers in their consumer drivers.

That doesn't work too well however, when a consumer device needs to deal
with multiple PHYs, or when multiple consumers need to deal with the same
PHY (a DSI driver and a CSI driver for example).

So we'll add a new interface, through two funtions, phy_validate and
phy_configure. The first one will allow to check that a current
configuration, for a given mode, is applicable. It will also allow the PHY
driver to tune the settings given as parameters as it sees fit.

phy_configure will actually apply that configuration in the phy itself.

Change-Id: I252cb7733740a28728e9ff228cba9a6b407b1b07
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry picked from commit aeaac93ddb)
 2020-11-10 12:53:05 +08:00
Sugar Zhang
01a9a1b00a ASoC: rockchip: i2s-tdm: Add mclk oe for rk3568 
Change-Id: I1c1e952ccabe7acf264746886fe468f3e2de418b
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2020-11-10 12:43:15 +08:00
Sugar Zhang
bf75307ae8 arm64: dts: rockchip: rk3568-evb: Add pinctrl for i2s1 
Change-Id: I4f8c3a8e4ccfa5b39fd2d41ae43c0cee7a28397c
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2020-11-10 12:38:07 +08:00
Sugar Zhang
3723d3c5c7 arm64: dts: rockchip: rk3568: Fix typo for spdif 
Change-Id: Ib05fc80c5f7c84f447f4774196c06d2a092e5925
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2020-11-10 12:34:29 +08:00
Wu Liangqing
ca955af676 arm64: dts: rockchip: rk3568-evb: set adc key val for esc and menu 
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
Change-Id: Icef74b2b5017804e2dbf85a79e8a3af7fbf3a955
 2020-11-10 11:52:18 +08:00
Guochun Huang
a84097bf1d drm/rockchip: dsi: add support dual-channel mode with independent PLL 
Display Pipeline:
                   ---> dsi0 --> dphy_tx0 --->
                  /                  |        \
                 /              dphy0_pll      \
      vp1/vp2 -->                               ---> panel
                 \              dphy1_pll      /
                  \                  |        /
                   ---> dsi1 --> dphy_tx1 --->


Change-Id: I9c975f29e2f40e04a1fac5c163aed0fa7cfb71e3
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
 2020-11-10 11:22:13 +08:00
Caesar Wang
bf443367b9 arm64/configs: update rockchip_linux_defconfig 
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I7d88aa1fdade5f72748eb7f279ffff1715c7eafc
 2020-11-10 11:19:31 +08:00
Tao Huang
85e59f5631 arm64: rockchip_defconfig: Add CONFIG_UNICODE 
Sync to gki_defconfig

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I3ec77a89d661e382f3c2efa1e210514af42ca37f
 2020-11-10 11:09:27 +08:00
Weixin Zhou
440e68c5ae arm64: dts: rockchip: rk3568-evb: adjust touch gt1x configuration 
Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
Change-Id: I06be23f54af5a37d556bcf0c2d8287e451df20b3
 2020-11-10 11:07:49 +08:00
Jianqun Xu
17a14a4451 pinctrl: rockchip: support output-high/low pin configure 
With this patch, the pinctrl driver will support output-high/ -low
pinconf, which passed from dts iomux nodes.

So the pinctrl module needs the gpio_chip which registered by gpio
module.

This patch makes the gpio driver use the rockchip_pin_bank from pinctrl,
after that, the pinctrl can call the gpiolib operations, include output.

Also do iomux check before call gpiolib operations, make sure that the
pin hasn't been used as other functions.

Change-Id: Iaba6f1ade8494235586d5e5ce52d6d497e072bc4
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2020-11-10 11:07:32 +08:00
Elaine Zhang
adb279b8e0 clk: rockchip: rk3568: fix up the vpll register address 
Fix up the error description of TRM.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I0a72c0c9d6070b53478e6a508fbc92c83a498c4b
 2020-11-10 10:08:03 +08:00
shengfei Xu
05e03831df arm64: dts: rockchip: rk3568-evb: set vcc_3v3/vcc3v3_sd always on 
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: Ieaae34bc4536cad8021b6ff3b4328c7e52b041cb
 2020-11-10 09:55:12 +08:00
Finley Xiao
cff325e000 clk: rockchip: rk3568: mark pclk_pmu as critical clk 
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I7edab6e751146e94fc9950da6d31837aa4f66260
 2020-11-09 22:46:00 +08:00
Andy Yan
80cd79aecb arm64: rockchip_defconfig: Disable DRM_FBDEV_EMULATION temporarily 
This will cause iommu fault as bellow:
Temporarily disable it before we have better solution.

[   10.015974] drm_mode_atomic_ioctl
[   10.016027] drm_atomic_set_property 0xcccccccc MODE_ID
[   10.016081] drm_atomic_set_property 0xcccccccc ACTIVE
[   10.016115] drm_atomic_set_property 0xcccccccc MODE_ID
[   10.016157] drm_atomic_set_property 0xcccccccc ACTIVE
[   10.016187] drm_atomic_set_property 0xcccccccc MODE_ID
[   10.016295] drm_atomic_set_property 0xcccccccc ACTIVE
[   10.016337] drm_atomic_set_property 0xc0c0c0c0 CRTC_ID
[   10.016390] drm_atomic_set_property 0xc0c0c0c0 CRTC_ID
[   10.016507] drm_atomic_helper_check
[   10.016716] vop2_plane_atomic_update Esmart1-win0
[   10.016781] vop2_crtc_atomic_flush iommu_enabled 1 iommu_needed :1
[   10.032142] rockchip_atomic_commit_complete
[   10.032205] drm_atomic_helper_cleanup_planes
[   10.032310] vop2_plane_cleanup_fb
[   10.032405] vop2_atomic_plane_destroy_state
[   10.032424] rockchip_gem_free_object
[   10.048738] rk_iommu fe043e00.iommu: Page fault at 0x0000000000030000
of type read
[   10.048791] rk_iommu fe043e00.iommu: iova = 0x0000000000030000:
dte_index: 0x0 pte_index: 0x30 page_offset: 0x0
[   10.048812] rk_iommu fe043e00.iommu: mmu_dte_addr: 0x000000007abd7000
dte@0x000000007abd7000: 0x7a01d001 valid: 1 pte@0x000000007
a01d0c0: 0x7a629006 valid: 0 page@0x0000000000000000 flags: 0x0
[   10.048870] [drm:rockchip_drm_fault_handler] *ERROR* iommu fault
handler flags: 0x28b
[   10.048902] Video Port0: DISABLED
[   10.048927]
[   10.048927] 0x00000000:
[   10.048931] 00008000
[   10.048956] 40158023
[   10.048981] 80000000
[   10.049008] 00000000
[   10.049034]
[   10.049034] 0x00000010:
[   10.049043] 00000ac0
[   10.049055] 00000000
[   10.049063] 00000000
[   10.049089] 00000000
[   10.049100]
[   10.049100] 0x00000020:
[   10.049122] 00000000
[   10.049147] e0000010
[   10.049172] 00010010
[   10.049196] 00000000

Change-Id: Id63a2f558f4ec096b405fad2f426dc525edc68b4
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-09 22:41:29 +08:00
Elaine Zhang
c838bda9d4 arm64: dts: rockchip: rk3568-evb: fix up the tcs4525 i2c address 
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I45bd9a617106eac475f2a701f92be38cbf2302f1
 2020-11-09 21:31:26 +08:00
Li Huang
d634d3c826 arm64: dts: rockchip: enable rga for rk3568-evb.dtsi 
Signed-off-by: Li Huang <putin.li@rock-chips.com>
Change-Id: I38e833e9595b846ac44a97faae567e747312c2d2
 2020-11-09 20:59:46 +08:00
Jianqun Xu
22f7f3bab6 pinctrl: rockchip: fix rk3568 pull reg offset 
Change-Id: I6656ad85ed87b0f545db90f86d247360c39b0227
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2020-11-09 20:55:55 +08:00
Hans Yang
b47ed7ce82 arm64: configs: rockchip_linux: Enable CONFIG_MMC_SDHCI_OF_DWCMSHC 
DesignWare based SDHCI controller will be used for eMMC on some
Rockchip platforms such as RK3568.

Signed-off-by: Hans Yang <yhx@rock-chips.com>
Change-Id: Icfc6b06d92267114bac44b06db96c923befee499
 2020-11-09 19:52:29 +08:00
Shawn Lin
e39465bb00 mmc: sdhci-of-dwcmshc: Fix HS400 and HS400es support 
Change-Id: I5e9e227e22e72730322ee6bf4441f0f224d55ece
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2020-11-09 18:16:12 +08:00
William Wu
4377dfe8a3 arm64: dts: rockchip: rk3568: add usb2 phy node for dwc3 otg controller 
Change-Id: I01028244afc6ff96ff5d23e413cabc4d8fded107
Signed-off-by: William Wu <william.wu@rock-chips.com>
 2020-11-09 18:06:47 +08:00
Elaine Zhang
5bf4066cad arm64: dts: rockchip: rk3568-evb: fix up the pmic_sleep active high 
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I3714cd412cd15bc66875f17ca830fb4dad877305
 2020-11-09 17:59:33 +08:00
Tao Huang
8894d8194d cpufreq: dt-platdev: Add rk3568 project into blacklist 
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ie269f0172e8b779455e46db75c38167716463f9d
 2020-11-09 17:30:37 +08:00
Hans Yang
e69fc71d35 arm64: dts: rockchip: rk3568-linux: add some bootargs 
add "root=" and rootwait boot option

Change-Id: I96d5a18b5d13a9ae2e5136c6b43b572369b7f531
Signed-off-by: Hans Yang <yhx@rock-chips.com>
 2020-11-09 17:25:09 +08:00
Andy Yan
64d0859286 drm/rockchip: vop2: Fix mipi pin/dclk polarity register defination 
Change-Id: Id674f00590e3f257b82620fb517d215fb56402f4
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-09 16:54:26 +08:00
Jianqun Xu
8b4a004041 arm64: configs: rockchip: disable DEBUG_GPIO 
Change-Id: I8d96858cb58a7ef4f1b72a77782e922d6d3174f5
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2020-11-09 16:27:15 +08:00
Jianqun Xu
f62099e346 ARM: configs: rockchip: disable DEBUG_GPIO 
Change-Id: Iecd8cfcfc79efcb4d7ee6cea424666f7396b1c3a
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2020-11-09 16:23:28 +08:00
Elaine Zhang
51db02c864 clk: rockchip: rk3568: fix up the vop dclk setting error 
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I629f699c133c2b395962321f2db9b5645f41c05a
 2020-11-09 16:14:47 +08:00
Tao Huang
2158ab7bba extcon: Create named extcon link nowarn 
Avoid warning:

[    0.366122] sysfs: cannot create duplicate filename '/class/extcon/usb2-phy'
[    0.366821] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 4.19.154 #120
[    0.367385] Hardware name: Rockchip RK3566 EVB1 DDR4 V10 Board (DT)
[    0.367945] Call trace:
[    0.368186]  dump_backtrace+0x0/0x15c
[    0.368520]  show_stack+0x14/0x1c
[    0.368830]  dump_stack+0xb8/0xf0
[    0.369139]  sysfs_warn_dup+0x68/0x80
[    0.369469]  sysfs_do_create_link_sd+0x90/0xc8
[    0.369870]  sysfs_create_link+0x2c/0x40
[    0.370227]  extcon_dev_register+0x5a4/0x6fc
[    0.370614]  devm_extcon_dev_register+0x44/0x84
[    0.371030]  rockchip_usb2phy_probe+0x26c/0xba4
[    0.371444]  platform_drv_probe+0x7c/0xb4
[    0.371813]  really_probe+0x488/0x520
[    0.372145]  driver_probe_device+0x60/0xf8
[    0.372520]  device_driver_attach+0x68/0xa4
[    0.372896]  __driver_attach+0xc0/0x13c
[    0.373249]  bus_for_each_dev+0x78/0xc0
[    0.373601]  driver_attach+0x20/0x28
[    0.373930]  bus_add_driver+0xfc/0x1dc
[    0.374271]  driver_register+0x74/0x108
[    0.374621]  __platform_driver_register+0x40/0x48
[    0.375049]  rockchip_usb2phy_driver_init+0x18/0x20
[    0.375486]  do_one_initcall+0x90/0x26c
[    0.375840]  do_initcall_level+0xbc/0x160
[    0.376203]  do_basic_setup+0x30/0x48
[    0.376533]  kernel_init_freeable+0xb0/0x134
[    0.376923]  kernel_init+0x14/0x290
[    0.377242]  ret_from_fork+0x10/0x18
[    0.377610] extcon extcon1: failed to create extcon usb2-phy link

Fixes: 513c60a1ba ("extcon: Add named extcon link")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ieac0e071b5bae8613aaf829a0aeed64ff6524ea2
 2020-11-09 15:39:02 +08:00
Guochun Huang
7edf3d7f18 arm64: dts: rockchip: rk3568-evb: set boot/always on for vcca1v8_image 
which supplying for EDP/HDMI/MIPI/LVDS TX AVDD

Change-Id: If2442ae2e37a6b49d8371c8955c3f9bd863559ae
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
 2020-11-09 15:27:08 +08:00
Liang Chen
f21a35d354 arm64: dts: rockchip: rk3568: add reboot-mode node 
Change-Id: I156488f2a58a74225e1f48e0c38a716dd32f13d8
Signed-off-by: Liang Chen <cl@rock-chips.com>
 2020-11-09 15:18:46 +08:00
Guochun Huang
99ec128b2b arm64: dts: rockchip: fix panel enable gpio for rk3566-evb1-ddr4-v10 
Change-Id: Ib57b31985d68b83c35ce3f0bb7b298aa469bfeff
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
 2020-11-09 14:08:49 +08:00
Guochun Huang
fa63fd7409 arm64: dts: rockchip: rk3568-evb: add attached panel for DSI 
Change-Id: Iadcc7d6d8a4838613627612a24628fbda6beca6c
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
 2020-11-09 14:08:00 +08:00
Ziyuan Xu
501432d789 ARM: dts: rv1126: set isp_tb reserver memory close to ramdisk_c 
Test on DDR 512MB

[    0.233910] OF: fdt: Reserved memory: reserved region for node 'trust@0': base 0x00000000, size 2048 KiB
[    0.233914] fdt_reserved_mem_save_node trust@0, 0-200000
[    0.233926] OF: fdt: Reserved memory: reserved region for node 'trust@200000': base 0x00200000, size 32 KiB
[    0.233930] fdt_reserved_mem_save_node trust@200000, 200000-8000
[    0.233948] OF: fdt: Reserved memory: reserved region for node 'ramoops@210000': base 0x00210000, size 960 KiB
[    0.233952] fdt_reserved_mem_save_node ramoops@210000, 210000-f0000
[    0.233966] OF: fdt: Reserved memory: reserved region for node 'rtos@300000': base 0x00300000, size 1024 KiB
[    0.233969] fdt_reserved_mem_save_node rtos@300000, 300000-100000
[    0.233982] OF: fdt: Reserved memory: reserved region for node 'ramdisk@2800000': base 0x02800000, size 49152 KiB
[    0.233986] fdt_reserved_mem_save_node ramdisk@2800000, 2800000-3000000
[    0.234000] OF: fdt: Reserved memory: reserved region for node 'ramdisk@5800000': base 0x05800000, size 20480 KiB
[    0.234003] fdt_reserved_mem_save_node ramdisk@5800000, 5800000-1400000
[    0.234017] OF: fdt: Reserved memory: reserved region for node 'rkisp@08000000': base 0x10000000, size 131072 KiB
[    0.234020] fdt_reserved_mem_save_node rkisp@08000000, 10000000-8000000
[    0.234033] OF: fdt: Reserved memory: reserved region for node 'mmc@20f000': base 0x0020f000, size 4 KiB
[    0.234036] fdt_reserved_mem_save_node mmc@20f000, 20f000-1000
[    0.234048] OF: fdt: Reserved memory: reserved region for node 'mmc@500000': base 0x00500000, size 1024 KiB
[    0.234052] fdt_reserved_mem_save_node mmc@500000, 500000-100000

For 4K camera, we should reserved 172MB CMA buffer for ISP. In this scenario,
the system can't find a free area that it's enough for 172MB.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: Ifc9ed49a337c91474842ab3a47783509d754e0d8
 2020-11-09 14:06:01 +08:00
David Wu
67f9244840 arm64: dts: rockchip: Fix the gmac interrupt-names for rk3568 
Change-Id: I0cb3693d73bd84793d108255f85039179042d658
Signed-off-by: David Wu <david.wu@rock-chips.com>
 2020-11-09 11:43:25 +08:00
Shawn Lin
b577a89078 mmc: sdhci-of-dwcmshc: Add proper clock and DLL control for rockchip 
Firstly we amend some wrong register definitions and add proper
clock and DLL control for rockchip platform. And we also remove
admac desc hook since we don't need this now.

Change-Id: Ib0b12f127c4d506fb92f27c84d97246e070fc864
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2020-11-09 11:41:11 +08:00
Shawn Lin
a35110c299 arm64: dts: rockchip: increase emmc clock to 200MHz for RK356X 
Change-Id: I49c3ef7fd553359f058a1dcc7731fba898df710a
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2020-11-09 11:41:11 +08:00
Shawn Lin
9365c1f93f arm64: dts: rockchip: remove CCLK_EMMC in sdhci node for rk356x 
We need change the rate via driver.

Change-Id: Id796ee74437ed40c8675012ef0b768ab0f6e7b4d
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2020-11-09 11:41:11 +08:00
Ding Wei
66b21e6052 video: rockchip: mpp: colmv issue for 3328 iommu pagefault 
Change-Id: Ia5ba4a5a1ebb17464ab0836b05ee2241efa682fd
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
 2020-11-09 11:05:38 +08:00
Tao Huang
d7a293d303 arm64: dts: rockchip: Temporarily disable its for rk3568 
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I975d132791b4ed746c59722e0e8e417ad05bcdfd
 2020-11-09 10:38:56 +08:00
Ziyuan Xu
7748d9ea0a ARM: dts: add rv1126 battery ipc board that IMX415(4K camera) inside 
It's same as rv1126-bat-ipc-v10 except camera.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I8ac4460d2dfb01e42120d235f2c93246509421c3
 2020-11-09 10:04:08 +08:00
Elaine Zhang
925dc1b993 clk: rockchip: rk3568: update the pmucru ref clk 
Pmucru updates missing parts of the TRM.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Idee0b51064c7579dfaeb03118e9d1eaae716d9e7
 2020-11-09 10:02:51 +08:00
William Wu
4a9087f17c phy: rockchip: naneng-combphy: refactor the combphy_reg and ops 
This patch refactor the combphy_reg so that we can init
PCIe/USB3.0/SATA/QSGMII separately.

Change-Id: I8febce777a5b29948acdb66a1640245983cfe6cd
Signed-off-by: William Wu <william.wu@rock-chips.com>
 2020-11-09 09:58:09 +08:00
Jianqun Xu
1d3ae33f1c pinctrl: rockchip: add rk3568 schmitt set support 
Change-Id: Id753492de3ab13104396cefa3b960b3fe28527e6
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2020-11-09 09:55:52 +08:00
shengfei Xu
6a3ca0144b arm64: dts: rockchip: fix init voltage for rk3568-evb 
Add regulator-init-microvolt for driver to init the regulator

Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: Ie967a0cccf63b3ff6966caedecdc58d469f08d2d
 2020-11-08 22:44:49 +08:00
Andy Yan
369e2fcb53 arm64: dts: rockchip: Enable vop/vop_mmu for rk3568-evb 
Change-Id: I46f9111193fe79dcfad9ddd301b44166526be672
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-08 22:09:35 +08:00
Shawn Lin
ebaa183ce2 mmc: sdhci-of-dwcmshc: Fix TX clock invert 
It should be in DWCMSHC_EMMC_DLL_TXCLK instead of
DWCMSHC_EMMC_DLL_RXCLK.

Change-Id: I24ffad485b64378cda42845c81f99698dd2b2edf
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2020-11-08 22:07:15 +08:00