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Author SHA1 Message Date
Sandy Huang
44ccff798b drm/bridge: synopsys: dw-hdmi-qp: add mode covert at dual_connector_split 
At split mode or dual connector split, the mode of horizontal direction
must x2.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I4583cb575c6714796b63c3dc312eb3c23319b116
 2024-09-19 11:03:20 +08:00
Finley Xiao
885afdcd0e PM / devfreq: rockchip_dmc: Fix dev_pm_opp_get_opp_table() return value 
Change-Id: I8a3f293bdfc17574735365e5049bdf47ce321770
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2024-09-19 10:55:47 +08:00
Finley Xiao
8ceb525d09 soc: rockchip: opp_select: Fix dev_pm_opp_get_opp_table() return value 
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I2f3b2bb6ccf359574a0b8d503f3491d9fa7e2299
 2024-09-19 10:33:24 +08:00
Finley Xiao
b6c6cd2b3a soc: rockchip: system_monitor: Fix dev_pm_opp_get_opp_table() return value 
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ia1db3e6087f57c4d804da779059584c56610e9ef
 2024-09-19 10:31:56 +08:00
Ye Zhang
faaec9bb5d ARM: dts: rockchip: rk3506: set DS of pwm pins to level1 
According to SI report, the default driver strength should be level1.

Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I2d10de82d9b836a479b38b782732a95f79079deb
 2024-09-18 17:30:32 +08:00
Ye Zhang
87108d5ab4 ARM: dts: rockchip: rk3506-pinctrl: Fix driver strengths of some SPI IOs 
Fixes: 68cf3d9c46 ("ARM: dts: rockchip: rk3506-pinctrl: Increase driver strengths of some SPI IOs")
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I0e0d75ab72b0a80853437cb9c2dde53bc87c8dd3
 2024-09-18 17:30:21 +08:00
Zain Wang
38049431f3 ARM: configs: rk3506: Separate modules configs from defconfig 
Separate modules:
1. rk3506-display.config
2. rk3506-ethernet.config
3. rk3506-wifibt.config
4. rk3506-usb-host.config
5. rk3506-usb-peripheral.config
6. rk3506-usb-otg.config

Keep 'm' value to these modules in rk3506_defconfig.

Change-Id: I74d77a29ed6e133e45f1a8cf1c7e9ca46509fe21
Signed-off-by: Zain Wang <wzz@rock-chips.com>
 2024-09-18 17:16:44 +08:00
Zain Wang
b3b9046ec5 usb: dwc2: fix compile error in USB_DWC2_HOST mode 
If enabled CONFIG_USB_DWC2_HOST, we will get error:

drivers/usb/dwc2/platform.c: In function ‘dwc2_resume’:
drivers/usb/dwc2/platform.c:825:12: error: ‘struct dwc2_hsotg’ has no member named ‘driver’
  825 |   if (!dwc2->driver)
    |            ^~

This is the code for periperal mode, add a macro to
remove them from CONFIG_USB_DWC2_HOST.

Change-Id: Ib2b9622d5cfe5e4c9329030fa10e0635b1aa7fb8
Signed-off-by: Zain Wang <wzz@rock-chips.com>
 2024-09-18 17:12:07 +08:00
Guochun Huang
db4eb2bcf1 drm/rockchip: dp: extcon sync for audio in .loader_protect helper 
Type: Fix
Redmine ID: #506052
Associated modifications: gerrit links
 Test: test method

Change-Id: I114679d477f33f0a6d8b13d0f72d9c36c41fc40c
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
 2024-09-18 14:05:13 +08:00
Guochun Huang
0e7febeb4a drm/rockchip: drv: mv show logo after drm_dev registered 
execution of extcon_set_state_sync() within the DP driver’s
.loader_protect helper failed due to dp->audio->extcon not
being allocated in dw_dp_single_audio_init() yet, which resulted
in the audio not work when the power-on logo feature is enabled.
so mv drm_dev_register() before rockchip_drm_show_logo().

Call trace:

  dw_dp_single_audio_init+0xc8/0x194
    dw_dp_encoder_late_register+0x28/0xa8
      drm_encoder_register_all+0x40/0x5c
	drm_modeset_register_all+0x38/0x7c
	  drm_dev_register+0x264/0x2e0
	    rockchip_drm_bind+0x1ec/0x2c8

Type: Fix
Redmine ID: #506052
Associated modifications: gerrit links
Test: test method

Change-Id: I1109a5ed90ac1c36028e050c41349c316d74e859
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
 2024-09-18 14:04:51 +08:00
Damon Ding
b6270dfe78 drm/rockchip: rgb: add dclk delayline configs for rk3506 
Remove redundant parameter passing for 'dclk_delayline', and dclk
delayline configs may be different between bt1120/bt656 and rgb
display interface.

Change-Id: I77b78665a1403ad9d39929b39811069f0ecc130e
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
 2024-09-18 10:16:58 +08:00
Yandong Lin
22c5e525ac video: rockchip: mpp: add devices load statistics 
1.The default statistical time is 0, means the load statistics function
is disabled.
If want to enable the function, need echo a valid value to
load_interval.
e.g. 1000ms:
$echo 1000 > /proc/mpp_service/load_interval

2.show load info:
rk3588_t_evb7:/ # cat /proc/mpp_service/load
fdb51000.avsd-plus        load:   0.00% utilization:   0.00%
fdb50400.vdpu             load:   0.00% utilization:   0.00%
fdb50000.vepu             load:   0.00% utilization:   0.00%
fdb90000.jpegd            load:   0.00% utilization:   0.00%
fdba0000.jpege-core       load:   0.00% utilization:   0.00%
fdba4000.jpege-core       load:   0.00% utilization:   0.00%
fdba8000.jpege-core       load:   0.00% utilization:   0.00%
fdbac000.jpege-core       load:   0.00% utilization:   0.00%
fdbb0000.iep              load:   0.00% utilization:   0.00%
fdbd0000.rkvenc-core      load:  97.56% utilization:  93.45%
fdbe0000.rkvenc-core      load:  97.33% utilization:  92.51%
fdc38100.rkvdec-core      load:   0.00% utilization:   0.00%
fdc48100.rkvdec-core      load:   0.00% utilization:   0.00%
av1d-master               load:   0.00% utilization:   0.00%

Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I0b1c6d3efc7cd7708e7f367ad917b865db67a08a
 2024-09-14 14:47:21 +08:00
Damon Ding
14dac2f903 ARM: dts: rockchip: rk3506g-evb1: fix pinctrl of rgb for mcu display board 
Fix the pinctrl of rgb to 'mcu_rgb565_pins', because the driver
strength configs of rgb and mcu are different for rk3506.

Change-Id: I488cdfd13e42c862be0f8ecd10bab215e87e87b8
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
 2024-09-13 15:49:55 +08:00
Damon Ding
af73c672cb ARM: dts: rockchip: rk3506: modify default DS level for vop pinctrl configs 
According to SI report, default drive strength of vop pinctrl
configs should be improved as described below:

bt1120/bt656:
CLK              level4
DATA             level2

mcu:
RS/WEN/CS/REN    level2
DATA             level0

rgb:
CLK              level3
HSYNC/VSYNC/DEN  level2
DATA             level2

Add a set of pinctrl configs which named "mcu_*", because the
driver strength configs of rgb and mcu are different for rk3506.

Change-Id: Ide4dd04531d8760194ab745d2fb348c644f27c4f
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
 2024-09-13 15:49:55 +08:00
Ye Zhang
4dc35e3247 thermal: rockchip: Add trim temperature for rk3576 
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I6ba9a60fb389b12a6d63ea3b19e271cf9d5ecad5
 2024-09-12 19:41:01 +08:00
Ye Zhang
3e7349667d arm64: dts: rockchip: rk3576: Fix trim configure for tsadc 
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: Id7399f84a7d3f75213528c89151efe1862b1b02e
 2024-09-12 19:40:42 +08:00
Sugar Zhang
2b6899e2d0 ASoC: rockchip: sai: Fix mclk check 
Before:
rockchip-sai ff810000,sai: mismatch mclk: 12287999, expected 0 (+/- 5Hz)

After:
rockchip-sai ff810000,sai: mismatch mclk: 12287999, at least 24576000

Fixes: 1831ca1cdc ("ASoC: rockchip: sai: Fix mclk rate check")

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I7addcf70104515c50463a42fc9fd7fe46a9456fd
 2024-09-12 18:08:29 +08:00
Sugar Zhang
f4e6d5530a ASoC: rockchip: sai: Add support lanes parsed from DT 
used to assign lanes from DT.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I2064b201a8325e0b5d1e7a448a14345443a173a4
 2024-09-12 18:08:29 +08:00
Zheng zhiqi
3fa1e010c7 arm64: dts: rockchip: rk3576-vehicle-evb: change sai1 channel 
Change sai1 tx 3 lanes, rx 2 lanes

Change-Id: If3d87aeec5382ea7a55163cd97031dd196021ce9
Signed-off-by: Zheng zhiqi <looper.zheng@rock-chips.com>
 2024-09-12 15:43:47 +08:00
Zheng zhiqi
e7d061526b arm64: dts: rockchip: rk3576-vehicle-evb-v20: change sai1 channel 
Change sai1 tx 3 lanes, rx 2 lanes

Change-Id: If68d799789490fce0ecb5da55c4b9dbe1fa7591a
Signed-off-by: Zheng zhiqi <looper.zheng@rock-chips.com>
 2024-09-12 15:43:47 +08:00
Zhen Chen
d1b62d2e45 MALI: rockchip: upgrade bifrost DDK to g25p0-00eac0, from g24p0-00eac0 
mali_csffw.bin from Valhall DDK g25(r50) is included.

Change-Id: Ic454428c384456a14b29d9651f537eb59c11284d
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
 2024-09-12 10:52:10 +08:00
Zhen Chen
4cedc115fd MALI: rockchip: upgrade bifrost DDK to g24p0-00eac0, from g22p0-01eac0 
mali_csffw.bin from Valhall DDK g24(r49) is included.

Change-Id: Ic48b63e744457163fbae3f41b477fc2827a1380e
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
 2024-09-12 10:52:10 +08:00
YouMin Chen
f8fff854d7 PM / devfreq: rockchip_dmc: ignore notifier during dmcfreq suspend 
Do not allow changes to frequency and voltage after dmcfreq enter suspend.

Change-Id: Ide146cfd49d77ee7dff88bd3b9eeb2e5d2ec82c0
Signed-off-by: YouMin Chen <cym@rock-chips.com>
 2024-09-12 10:13:05 +08:00
YouMin Chen
2961e8dde5 PM / devfreq: rockchip_dmc: update dmcfreq->volt in rockchip_dmcfreq_set_volt 
Update dmcfreq->volt within the rockchip_dmcfreq_set_volt function to avoid
uninitialized use errors that may occur during rockchip_dmcfreq_resume().

Change-Id: I1fd3303df5adf2837b994b4fee31848864d4dccd
Signed-off-by: YouMin Chen <cym@rock-chips.com>
 2024-09-11 19:44:58 +08:00
Xing Zheng
f981c02164 ARM: rk3506_defconfig: enable SND_PCM_TIMER by default 
The plugins of dsnoop/dmix will be fault if this config is disable:
----
root@rk3506-buildroot:/etc# arecord -Ddefault -c 2 -r 16000 -fS16_LE /tmp/record.wav -vv
ALSA lib pcm_direct.c:1504:(snd1_pcm_direct_initialize_poll_fd) unable to open timer 'hw:CLASS=3,SCLASS=0,CARD=0,DEV=0,SUBDEV=1'
ALSA lib pcm_dsnoop.c:643:(snd_pcm_dsnoop_open) unable to initialize poll_fd
arecord: main:850: audio open error: No such file or directory

Therefore, we needs to enable it.

before:
   text	   data	    bss	    dec	    hex	filename
4934889	2270232	 114496	7319617	 6fb041	vmlinux
after:
   text	   data	    bss	    dec	    hex	filename
4944910	2272032	 114944	7331886	 6fe02e	vmlinux

Change-Id: I669e50141957546f35b3a0ede3e1b7928ca14b9c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
 2024-09-11 18:36:34 +08:00
Algea Cao
399bc0fb97 drm/rockchip: dw_hdmi: Set rk3588 hpd low level count threshold value to 2ms 
The default hpd low level count threshold value is 100ms.
This means that the hpd being pulled down must last for 100ms
then hpd interrupt is triggered. This can cause the hpd
status to be misjudged in some scenarios.

Change-Id: I1999b0dd37e5f1dae2c2f35c7a84dd07efc77f03
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
 2024-09-11 17:12:04 +08:00
Damon Ding
01bd3d2b6a ARM: dts: rockchip: rk3506g-evb1: modify the mcu timing according to SI report 
According to the SI report, the new mcu timing can meet
the signal needs for panel k350c4516t.

Change-Id: Ie6b72cdc97a676795dcb7ed44f93826e0d37dadc
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
 2024-09-11 17:10:42 +08:00
Damon Ding
16c29be105 ARM: dts: rockchip: rk3506g-evb1: add read cmds and bypass timing for mcu display board 
Read Read ID4(D3h) from panel K350C4516T for debug in
initialization process.

Change-Id: Ia5ecd6b22074ede496b898c8ad5dbcbafb6e7601
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
 2024-09-11 17:10:42 +08:00
XiaoDong Huang
247f5deabf soc: rockchip: pm_config: replace memset with memset_io 
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ia75fbfba4efd9d10eb2d15f5ae646135d858e0a0
 2024-09-11 16:53:41 +08:00
Lin Jinhan
629aef9788 crypto: rockchip: set CRYPTO_ALG_INTERNAL for cra_flags 
Rockchip's crypto driver is set to the CRYPTO_ALG_INTERNAL flag,
 which prevents it from being called by other modules of the system
 and is only used for librkcrypto use.

Fixed the panic bug caused by calling hmac(sha256) in Android CTS test:

[  234.124644][    C0] ------------[ cut here ]------------
[  234.124694][    C0] kernel BUG at arch/arm64/kernel/fpsimd.c:1832!
[  234.124708][    C0] Internal error: Oops - BUG: 00000000f2000800 [#1] PREEMPT SMP
[  234.165910][    C0] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G           OE      6.1.78-android14-11-g55b024554aae-ab11965736 #1
[  234.166912][    C0] Hardware name: Rockchip RK3576 EVB1 V10 Board (DT)
[  234.167486][    C0] pstate: 404000c5 (nZcv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[  234.168160][    C0] pc : kernel_neon_begin+0xe8/0x14c
[  234.168623][    C0] lr : cbc_decrypt+0x94/0x104
[  234.169037][    C0] sp : ffffffc008003ce0
[  234.169393][    C0] x29: ffffffc008003ce0 x28: ffffffc009faed80 x27: 00000000000000e0
[  234.170093][    C0] x26: ffffffc00a13e000 x25: 0000000000000001 x24: ffffff800dd85dc0
[  234.170792][    C0] x23: ffffff80f17e5540 x22: ffffff80f17e5600 x21: 0000000000000002
[  234.171492][    C0] x20: ffffff80c3720d70 x19: ffffffc009faed80 x18: ffffffc008005060
[  234.172192][    C0] x17: 000000000000003c x16: 000000000000003c x15: 000000000000003c
[  234.172891][    C0] x14: 0000000000000000 x13: fffffffe030dc9c0 x12: 000000000000003c
[  234.173590][    C0] x11: 000000000000003c x10: 0000000000000008 x9 : 0000000000000080
[  234.174289][    C0] x8 : 00000000000000c0 x7 : 0000000000000000 x6 : 189055e08898eccd
[  234.174988][    C0] x5 : 000000000000003c x4 : 0000000000000fc4 x3 : 0000000000000020
[  234.175687][    C0] x2 : 0000000000000030 x1 : 0000000000000020 x0 : 0000000000000000
[  234.176387][    C0] Call trace:
[  234.176667][    C0]  kernel_neon_begin+0xe8/0x14c
[  234.177092][    C0]  cbc_decrypt+0x94/0x104
[  234.177472][    C0]  crypto_skcipher_decrypt+0x3c/0x54
[  234.177932][    C0]  crypto_authenc_decrypt_tail+0xd8/0xf4
[  234.178423][    C0]  authenc_verify_ahash_done+0x5c/0x6c
[  234.178902][    C0]  rk_ahash_crypto_complete+0x10c/0x204 [rk_crypto]
[  234.179522][    C0]  rk_complete_op+0x78/0x100 [rk_crypto]
[  234.180049][    C0]  rk_crypto_done_task_cb+0xc8/0x100 [rk_crypto]
[  234.180641][    C0]  tasklet_action_common+0x260/0x4bc
[  234.181100][    C0]  tasklet_action+0x24/0x34
[  234.181492][    C0]  __do_softirq+0x11c/0x418
[  234.181883][    C0]  ____do_softirq+0x10/0x20
[  234.182274][    C0]  call_on_irq_stack+0x3c/0x74
[  234.182687][    C0]  do_softirq_own_stack+0x1c/0x2c
[  234.183121][    C0]  __irq_exit_rcu+0x54/0xb4
[  234.183513][    C0]  irq_exit_rcu+0x10/0x1c
[  234.183893][    C0]  el1_interrupt+0xa4/0xd8
[  234.184276][    C0]  el1h_64_irq_handler+0x18/0x24
[  234.184710][    C0]  el1h_64_irq+0x68/0x6c
[  234.185079][    C0]  cpuidle_enter_state+0x1d0/0x5b4
[  234.185526][    C0]  cpuidle_enter+0x38/0x54
[  234.185905][    C0]  do_idle+0x1d4/0x294
[  234.186268][    C0]  cpu_startup_entry+0x34/0x3c
[  234.186682][    C0]  rest_init+0xe0/0xe4
[  234.187042][    C0]  arch_call_rest_init+0x10/0x14
[  234.187477][    C0]  start_kernel+0x384/0x478
[  234.187866][    C0]  __primary_switched+0xc8/0xd4
[  234.188295][    C0] Code: f85f8e5e d65f03c0 943f17c6 34fffcd5 (d4210000)
[  234.188891][    C0] ---[ end trace 0000000000000000 ]---
[  234.204980][    C0] Kernel panic - not syncing: Oops - BUG: Fatal exception in interrupt

Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I9bace812173c232f16fd8cb72466d37fae98a5b6
 2024-09-11 16:08:44 +08:00
Xuhui Lin
ad889adf73 spi: rockchip: Increase transfer completion wait time 
Increase the transfer completion wait time to 4 seconds.

Change-Id: I0bc56ac219f3b470b2184e3411ccdadfc9a7f5ac
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
 2024-09-11 09:39:04 +08:00
Jianwei Fan
c3f682ec2b media: i2c: tc35874x: fix 5V event report 
Change-Id: I61c9b15f662b9e132bcf54b06866df3d873be880
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
 2024-09-10 19:54:17 +08:00
Jianwei Fan
5d9b65e8a7 media: i2c: tc35874x: add RKMODULE_GET_HDMI_MODE ioctl 
Change-Id: Ia3952f78b03c7947de8f94174f35180e2d32c270
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
 2024-09-10 19:54:17 +08:00
Zheng zhiqi
1a5486e7e7 arm64: dts: rockchip: rk3588-vehicle-evb: add spi0:1 dev 
Open spi0:1 dev for audio, control adsp

Change-Id: I9311edbd7ddb29ee213861a08ae2ab4f5ef64f53
Signed-off-by: Zheng zhiqi <looper.zheng@rock-chips.com>
 2024-09-10 16:20:11 +08:00
Shunhua Lan
73b0179081 arm64: dts: rockchip: rk3588: set i2s wait time for i2s7 used in hdmiin audio 
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
Change-Id: Ib752c6c7e5a09aa6cf6ce1e605419eb43b062831
 2024-09-10 14:12:55 +08:00
Shunhua Lan
379725d118 arm64: dts: rockchip: rk3588-evb7-v11-rk628-hdmi2csi: set i2s wait time for i2s3 used in rk628 hdmiin audio 
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
Change-Id: Ia866c9a4b1085d29c4adfd70a10075d64df03b55
 2024-09-10 11:08:34 +08:00
Chen Shunqing
c0e0c0e05f media: i2c: rk628: fix problem of false trigger signal change 
Type: Fix
Redmine ID: #503357
Associated modifications: N/A
Test: N/A

Signed-off-by: Chen Shunqing <csq@rock-chips.com>
Change-Id: I15657cf8b6fc729fe08061c73a5f13362aad288d
 2024-09-06 11:27:32 +08:00
Chen Shunqing
de3d3362d4 media: i2c: rk628: add interface for setting edid by version 
Signed-off-by: Chen Shunqing <csq@rock-chips.com>
Change-Id: I1d07d025a60e3ddbd0d77cba885c501b6b8a245d
 2024-09-06 11:27:27 +08:00
Zhihuan He
afd515fb5e memory: rockchip: dsmc: add data training for dll 
Change-Id: I8b54fd9276f2680fbc3b2b66c9a81a58c18668cd
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
 2024-09-06 11:09:17 +08:00
Zhihuan He
4f418e6887 memory: rockchip: dsmc: modify DMA API to interleaved 
Change-Id: I5e7404388e8d916ee3e2796bde22ac272ac265d7
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
 2024-09-06 11:09:17 +08:00
Zhihuan He
ffd1dbd70c ARM: rk3506_defconfig: Enable DSMC and DSMC_SLAVE configs 
Change-Id: Ie887a72a7e26032d27ba8a193f67f48d04deb1cb
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
 2024-09-05 20:29:50 +08:00
Zhihuan He
06ef7e6dc3 memory: rockchip: dsmc: add dsmc local bus slave driver 
Change-Id: Icf4c4abe11595d4069e36265db5441f52593896a
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
 2024-09-05 20:29:50 +08:00
Shuangjie Lin
736d89f344 driver: rknpu: Update rknpu driver, version: 0.9.8 
* Fix muti-process run error
* Fix mult-process domain switch error

Signed-off-by: Shuangjie Lin <shuangjie.lin@rock-chips.com>
Change-Id: I3052eca6ef577dc6420dd4c80a3ac7d0f17211ba
 2024-09-05 20:21:54 +08:00
Jason Zhu
c465ea7656 ARM: dts: rockchip: rk3506: add asrc node 
Change-Id: I306053f2db038f61f49d224cece8809ec213e838
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
 2024-09-05 20:05:32 +08:00
Jason Zhu
64b3855098 ASoC: rockchip: asrc: support rk3506 asrc 
Change-Id: Icc872b5ca37fbba0f43a6a088871c4d6dc96ab43
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
 2024-09-05 20:04:50 +08:00
Zhihuan He
a57c7b16a9 ARM: dts: rockchip: Add rk3506-evb1 dsmc-lb-slave demo 
Change-Id: I483819fa566c0b68f4df9f4aba44dc9369c634c8
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
 2024-09-04 17:50:56 +08:00
Zhihuan He
87315bab6b memory: rockchip: dsmc: add rk3506 support 
Change-Id: I11459d02100fd388ffeae11685a58ec5620e5bf6
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
 2024-09-04 17:47:25 +08:00
Zhihuan He
b76d37e906 ARM: dts: rockchip: Add rk3506-evb1 dsmc master demo 
Change-Id: I68d423ad8fa49a030055c71ff6a84305cb03e1e2
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
 2024-09-04 17:46:46 +08:00
Cai YiWei
a4f6c3f71d media: rockchip: isp: support bytesperline set by user for rawrd video 
Change-Id: I8b3587dca548da163ae865221e706091223063fb
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2024-09-04 17:41:59 +08:00
Cai YiWei
afea4b4ef2 media: rockchip: isp: rawrd format sync with isp input format change 
Change-Id: Ic37ab5c9f4a712b2ab2232ad4c91ba2d7a415612
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2024-09-04 16:46:46 +08:00