Speed change is set via dw_pcie_setup_rc(), so if both of links
support gen2 or gen3, auto speed change will happen. However, if
it's not, provide a manual speed change for EP function driver.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ib0dc765452aef0723968c5d48b5b44de24ca141e
The GPIO1_C5 is multiplexed by VO_LCDC_D6, which needed by
bt1120/bt656/mcu/rgb, and USB20_OTG0_VBUSDET.
Enabling rockchip,vbus-always-on can make ADB work well without
the vbus detection pin.
Change-Id: I7fa705436cf8a1e41f0f61f4941c24f3d9f433b0
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The default hardware design of rk3506g-iotest does not support
USB VBUS detect, so add vbus-always-on property for u2phy.
Change-Id: I9a1a130333a1843335cf2e28c6b705197f086456
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Sync the cma size with mipi display board. It is needed to allocate
22MB cma to meet the rockit application requirements for rk3506.
Change-Id: I94005a69e17f9d0d6aaedee271ba507cc9596ea8
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
1 diff isp version iqtool copy buffer use the same function
2 iqtool before memcpy sync src_buf cache
Signed-off-by: Mingwei Yan <mingwei.yan@rock-chips.com>
Change-Id: I969481c3a59fbff6ec621402e4b19d1647345fde
The following errors are seen when wifi is running:
NOHZ tick-stop error: Non-RCU local softirq work is pending, handler #08!!!
Fix this problem by adding the BH locking around __napi_schedule, in the same way
it was done in commit e63052a5dd ("mlx5e: add add missing BH locking around napi_schdule()").
Change-Id: I25544b52460639ba95d3cbdd9644ab95f01a2654
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>
Fix the if condition logic in the rockchip_asrc_get_clk_parent
function by replacing the third "&&" with "||".
Change-Id: Ib5c00812bb72c0443ea9565e8d669f7a7fafd156
Signed-off-by: Zhong Shengquan <shengquan.zhong@rock-chips.com>
1. enable sai1 for TDM card
2. enable sai2 for BT card
3. enable sai4 for FA caard
4. enable spidev0.0 for audio control
Change-Id: Ib9a20936164d5ce5d82ba1736001c66eeaaa8b68
Signed-off-by: Zheng zhiqi <looper.zheng@rock-chips.com>
Check whether ipi/link/vid clk is enabled in
uboot to determine whether the uboot logo is
enabled.
Change-Id: I6da4b0694a3df5a48136c96fa21d5f98dcc8d7c7
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Fixes: 73d255eb3b ("nvmem: rockchip-otp: do not close common clk")
Change-Id: I7b73ac1e87bcdab04471eb8805f58fc6a438d7a4
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Fixes: 73d255eb3b ("nvmem: rockchip-otp: do not close common clk")
Change-Id: I719526a754bebbc705c6e283d014e8a7000de3ca
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Fixes: 73d255eb3b ("nvmem: rockchip-otp: do not close common clk")
Change-Id: I470ec453b67aca985dc04f31897ccab86f12d8ad
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Current code if the device is connected and do _dwc2_hcd_resume(),
it will goto unlock and exit this function, cause some dwc2
controllers that does not support Partial Power Down mode resume
failed and perform the following error log:
usb 2-1: reset high-speed USB device number 2 using dwc2
usb 2-1: device descriptor read/64, error -110
usb 2-1: device descriptor read/64, error -110
Fixes: c74c26f6e3 ("usb: dwc2: Fix partial power down exiting by
system resume")
Change-Id: I34d449f1286c8122883aedcd830f2744f1a2267d
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Fix the issue where the system will reboot when exporting the PHY
registers from user space through the following command:
cat /d/regmap/feda0000.phy-dcphy/registers
or
cat /d/regmap/fedb0000.phy-dcphy/registers
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I46f90a04d15a4e583238e966953bc70fb9c3c150
When the amount of data written increases, more space is allocated,
but when the amount of data written decreases, the allocated space
is reclaimed without updating the value of free_size.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Iecf2af482c1e8af35b9fa3227bcbb597d75f770d
Since the hardware bug of HUSB311, its TX fifo become abnormal
when plug in a PD charger after plug out the cable from the PC.
As a workaround, we do ResetTransmitBuffer after each TX packet
is finished to prepare for the next.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Ieebd090879a45ee2b5a1720e3debf860712e162c
At split mode or dual connector split, the mode of horizontal direction
must x2.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I4583cb575c6714796b63c3dc312eb3c23319b116
According to SI report, the default driver strength should be level1.
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I2d10de82d9b836a479b38b782732a95f79079deb
Separate modules:
1. rk3506-display.config
2. rk3506-ethernet.config
3. rk3506-wifibt.config
4. rk3506-usb-host.config
5. rk3506-usb-peripheral.config
6. rk3506-usb-otg.config
Keep 'm' value to these modules in rk3506_defconfig.
Change-Id: I74d77a29ed6e133e45f1a8cf1c7e9ca46509fe21
Signed-off-by: Zain Wang <wzz@rock-chips.com>
If enabled CONFIG_USB_DWC2_HOST, we will get error:
drivers/usb/dwc2/platform.c: In function ‘dwc2_resume’:
drivers/usb/dwc2/platform.c:825:12: error: ‘struct dwc2_hsotg’ has no member named ‘driver’
825 | if (!dwc2->driver)
| ^~
This is the code for periperal mode, add a macro to
remove them from CONFIG_USB_DWC2_HOST.
Change-Id: Ib2b9622d5cfe5e4c9329030fa10e0635b1aa7fb8
Signed-off-by: Zain Wang <wzz@rock-chips.com>
execution of extcon_set_state_sync() within the DP driver’s
.loader_protect helper failed due to dp->audio->extcon not
being allocated in dw_dp_single_audio_init() yet, which resulted
in the audio not work when the power-on logo feature is enabled.
so mv drm_dev_register() before rockchip_drm_show_logo().
Call trace:
dw_dp_single_audio_init+0xc8/0x194
dw_dp_encoder_late_register+0x28/0xa8
drm_encoder_register_all+0x40/0x5c
drm_modeset_register_all+0x38/0x7c
drm_dev_register+0x264/0x2e0
rockchip_drm_bind+0x1ec/0x2c8
Type: Fix
Redmine ID: #506052
Associated modifications: gerrit links
Test: test method
Change-Id: I1109a5ed90ac1c36028e050c41349c316d74e859
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Remove redundant parameter passing for 'dclk_delayline', and dclk
delayline configs may be different between bt1120/bt656 and rgb
display interface.
Change-Id: I77b78665a1403ad9d39929b39811069f0ecc130e
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Fix the pinctrl of rgb to 'mcu_rgb565_pins', because the driver
strength configs of rgb and mcu are different for rk3506.
Change-Id: I488cdfd13e42c862be0f8ecd10bab215e87e87b8
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
According to SI report, default drive strength of vop pinctrl
configs should be improved as described below:
bt1120/bt656:
CLK level4
DATA level2
mcu:
RS/WEN/CS/REN level2
DATA level0
rgb:
CLK level3
HSYNC/VSYNC/DEN level2
DATA level2
Add a set of pinctrl configs which named "mcu_*", because the
driver strength configs of rgb and mcu are different for rk3506.
Change-Id: Ide4dd04531d8760194ab745d2fb348c644f27c4f
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
