dclk_vop_frac is frac divider with high jitter,
Is unfriendly to vop.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: If6218886fe64182261cf37172c88fcaeea197b22
Fixes: 389088186f ("soc: rockchip: rockchip_system_monitor: Use new APIs to check rate and volt")
Change-Id: I252146bb541c4de97a0a4c72546842353c712318
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This implements new APIs to get soc info and set opp hardware info.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I167a37f661ce6fc8b32afc7768985fe23e35318c
* commit 'fbd35aede4e2c60a1557bd824a4a194893d93695':
cpufreq: rockchip: set supported hw version for opp
driver: rknpu: Update rknpu driver, version: 0.9.1
media: i2c: sc301iot: pm runtime put device until stream off for thunderboot
drm/rockchip: dw-dp: support hdcp key without aes encrypt
video: rockchip: mpp: fix session cleanup issue
media: i2c: sc3338 support normal boot
arm64: dts: rockchip: rk3588-vehicle-evb-v21: change pcie wifi power control
arm64: dts: rockchip: rk3308bs-evb-mipi-display-v11: reduce drive strength of lcdc d18~23 from 6ma to 2ma
ARM: dts: rockchip: rv1106g-evb2-v10: correct sc3338 gpio
phy: rockchip-typec: use phy interface replace global functions
drm/rockchip: cdn-dp: use phy interface replace global functions
phy: rockchip-typec: Fix DP lane config
Conflicts:
drivers/cpufreq/rockchip-cpufreq.c
Ignore:
commit fbd35aede4 ("cpufreq: rockchip: set supported hw version for opp")
Change-Id: Ib0a67c2e034e9863bd8a02a4ee032c3c10971078
* commit '6397c9ae572a61003dde39d2563c487bf12a0dc9':
drm/rockchip: cdn-dp: support dp training outside dp firmware
drm/rockchip: cdn-dp: Avoid drm_dp_link helpers in dp training
FROMLIST: drm/rockchip: add transfer function for cdn-dp
Conflicts:
drivers/gpu/drm/rockchip/cdn-dp-core.c
drivers/gpu/drm/rockchip/cdn-dp-core.h
Ignore:
0aefe26fd9 ("FROMLIST: drm/rockchip: add transfer function for cdn-dp")
99b9c4c771 ("drm/rockchip: cdn-dp: Avoid drm_dp_link helpers in dp training")
6397c9ae57 ("drm/rockchip: cdn-dp: support dp training outside dp firmware")
Change-Id: I1c17714963639b3ea88418ddd8ad43e88327d0ec
DP firmware uses fixed phy config values to do training, but some
boards need to adjust these values to fit for their unique hardware
design. So get phy config values from dts and use software link training
instead of relying on firmware, if software training fail, keep firmware
training as a fallback if sw training fails.
Change-Id: I075bff6aa153a5e18b6a5ddec2645131f1411913
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
drivers/gpu/drm/panel/panel-maxim-max96772.c:22:10: fatal error: drm/drm_dp_helper.h: No such file or directory
drivers/gpu/drm/panel/panel-maxim-max96772.c:536:19: error: initialization of 'void (*)(struct i2c_client *)' from incompatible pointer type 'int (*)(struct i2c_client *)'
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I53cd11e89b92a96e5724db344c86709c2ca414ff
* commit 'a9ed7b93e657b49420dc7c02c3ce9ce810e9b7d3':
media: rockchip: vicap compatible with rk3588s2
media: rockchip: vicap support combine two mipi to one dev
phy: rockchip: csi2-dphy: logic node of mipi phy can control all hw of mipi phy
Conflicts:
drivers/phy/rockchip/phy-rockchip-csi2-dphy.c
Ignore:
commit 08330d500d ("phy: rockchip: csi2-dphy: logic node of mipi phy can control all hw of mipi phy")
Change-Id: Ief48fe16863dc477a183289f9a4c49881d2d2942
* commit 'c929ccacbb38fb047ca64ffee41ca4ab43f324eb':
include: rk-camera-module: support get/set capture info
include: rkcif-config: support set multi csi info
ARM: dts: rockchip: rv1106 separate the node of csi2 and hw
ARM: dts: rockchip: rv1126 separate the node of csi2 and hw
arm64: dts: rockchip: rk1808 separate the node of csi2 and hw
arm64: dts: rockchip: rk3562 separate hw node of mipi csi2 and mipi dphy
arm64: dts: rockchip: rk3568 separate the node of csi2 and hw
arm64: dts: rockchip: rk3588 separate the node of csi2 logic and hw
arm64: dts: rockchip: rk3588 mipi dphy config modify
Conflicts:
arch/arm64/boot/dts/rockchip/rk3568.dtsi
Ignore:
commit 841fa2175d ("arm64: dts: rockchip: rk3568 separate the node of csi2 and hw")
Change-Id: If60dc34bbe2d753ff36a3325cb5a648b1f80169d
* commit '328145662f6d6154fbf4329a0d53f9c152673648':
mtd: spinand: skyhigh: The vendor requires the devices to be patched
mtd: spinand: foresee: Support new device F35UQA001G-WWT
mtd: spinand: foresee: Support new device F35UQA002G-WWT
mtd: spinand: fmsh: Support new device FM25S01BI3
mtd: spinand: fmsh: Modify incorrect information despite not used
drm/bridge: analogix_dp: add support split area prop
drm/rockchip: dsi2: add support split area prop
drm/rockchip: analogix_dp: support split mode with other display interface
drm/bridge: analogix_dp: support dual connector with other display interface
drm/rockchip: dsi2: support split mode with other display interface
drm/rockchip: drv: Add crtc_clock convert in drm_mode_convert_to_{split,origin}_mode()
drm/bridge: analogix_dp: mv mode_set to bridge .atomic_pre_enable
drm/rockchip: dsi2: mv mode set to encoder .atomic_enable
Change-Id: Ie34682a12a9877c582fc95803edcf527ccdae98e
Conflicts:
drivers/mtd/nand/spi/core.c
Ignore:
commit 328145662f ("mtd: spinand: skyhigh: The vendor requires the devices to be patched")
Change-Id: I5baf8f1296e43b3491994529cb8b4ac1f08b3cf4
1.Double OIP=0 after page 13H
2.The nand flash does not support 84H and 34H command
Change-Id: Ie805f42a36e1a864115988087bdc43592cc94ded
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Commit 000cbb7d4b ("UPSTREAM: usb: gadget: uvc: add scatter gather
support") use scatter gather transfers for uvc isoc. However, the patch
conflicts with rockchip's zero-copy code.
Fixes: 5452a06eed ("usb: gadget: uvc: support zero copy with rockchip encoder")
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Change-Id: I515d79610a9bba74bbf28b0be974b5081a4b3c76
Some device share one pd, but reset control are different.
It should share a reset_group to ensure that one device can
not do reset while anothor is running.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I53527a053d0835085522396e2d9ee649d78325a5
1/ The backlight is for the eDP panel and it has the connector on the
excavator baseboard.
2/ remove cdn_dp
Fixes: 5a2a93f1ee ("arm64: dts: rockchip: move backlight from rk3399 sapphire to excavator")
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I4de565a2658b9a26f7b4155fce03db875703fa0d
The max dclk rate of rgb interface is limited by lcdc
io rate, and that of mcu interface is limited by vop
input rate.
In addition, modify the check of mcu panel, and replace
the flag is_mcu_panel by np_mcu_panel.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I329715aff21f67baf0187cb06b31ffb65f2e9517
rtc compensation value needs to be converted to a bcd code.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ic24a5ba0c31c42b804d1efa65702e680bae26630
Add some delay for some broken card which need long time to
release the remain power leak. 200ms is very safe, no need to
bother device tree property, as it depends on card not board.
Fixes: 60c9e5240f ("mmc: dw_mmc: Add normal and idle pinctrl control")
Change-Id: I5437945cd860674be860d246200e15eed9d91e03
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
rkvdec2_link_power_off():
power_enabled = 0 -> disable irq -> power off
rkvdec2_link_irq():
if power_enabled == 0 -> return and not clear irq
there is a corner case:
1. after power_enabled flag set to 0 and before disable irq
2. irq coming
3. irq return and not clear irq
4. repeat step 2
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I284bf40acb19e0c48cf04e526a534fec6383eb11
In some platform, there are some devices share PD.
If one device is doing pmu idle request to cru reset and
at this time cpu want to read/write reg for the device will crash.
So use the reset_group to prevent the case.
There is a issue that reset_group protected range not enough,
so fix it.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: Ide32966f7cff842e4611213d26901617fd57bc14
If sample_flat field is set to 1, there can't be any sound.
Change-Id: I56ad87d1165fe7d1cc993f9522c4e6d50c253b80
Signed-off-by: Chen Shunqing <csq@rock-chips.com>
There is no length alignment requirement for the last scatterlist.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I9625bce9379cef4c1a8507ba523f5f303d60c9e6
If the time required for a single data calculation exceeds 3 seconds,
timeout occurs.The timeout timer should be reset after the CRYPTO irq
interrupt is triggered.
Change-Id: I21516ba57bfc8eef3b22624e4ed95523d000cee2
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
../drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/aiutils.c:25:10: fatal error: 'typedefs.h' file not found
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I425cb52776bb1b3294b8ef67c951b04afe2288a9
the deskew fifo works on its own pointers may cause inter-lane skew
to exceed the vesa standard, this poses a risk of errors in dp sink
parsing MSA packet which inserted in data stream
Change-Id: Ia3bdfaed8696c8f7f21f39f0b55d18b1dce7761f
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
For a more stable system, delete the 528MHz frequency and open
the 666MHz frequency ODT.
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I0354c6dde8f39a9b41878446475ee3acbe1be729
