We should judge the table.id[mid].code insearch algorithm on matter the
adc value increment or decrement.
Or otherwise, the temperature return the incorrect value in some cases.
[ 1.438589] adc_val=402,temp=-40000
[ 1.438903] adc_val=403,temp=-39375
[ 1.439217] adc_val=404,temp=-38750
...
[ 1.441102] adc_val=410,temp=-40000
[ 1.441416] adc_val=411,temp=-34445
[ 1.441737] adc_val=412,temp=-33889
...
Let's fix it right now.
Fixes commit 020ba95
"thermal: rockchip: Add the sort mode for adc value increment or decrement"
Change-Id: Icac84d06ebf463439ca11db5a19d629b4b2b865c
Reported-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
A GPIO was put in rk3399.dtsi that doesn't belong there. Specifically
this GPIO isn't the same for all rk3399 boards. I presume it belongs in
rk3399-tb.dts, so move it there.
Change-Id: I0b3272655da565eb6b348a33401f7517224db5fa
Fixes: 3ed499f07c ("ARM64: dts: rockchip: rk3399: add usb2.0 phy node")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
And removed:
----
-CONFIG_FB=y
-CONFIG_LCDC_RK3368=y
-CONFIG_LCDC_LITE_RK3X=y
-CONFIG_RK_IOMMU=y
-CONFIG_RK_IOVMM=y
----
which are unused on the chromeos.
Change-Id: Icd521b56b6285099d72d3bf25575466792b6d353
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
there will be a build failure when CONFIG_RK_IOMMU
disabled.
Change-Id: Ifd56e39b9cb3021f308f195087304a1d1ec2c599
Signed-off-by: alpha lin <alpha.lin@rock-chips.com>
add pwm init voltage and id for uboot.
fix up the pwms node and add pwm polarity.
Change-Id: I4159c97ae498411ab958c2b1e1223139ac670452
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Portage's linux-info.eclass (in getfilevar_noexec) looks for the
definition of SUBLEVEL, and it doesn't expect 2 definitions. We could
fix the eclass, but let's hack this out for now.
See strongswan's emerge output:
...
* Found sources for kernel version:
* 4.4.6
* 0
/mnt/host/source/src/third_party/portage-stable/eclass/linux-info.eclass: line 388: 6
0: syntax error in expression (error token is "0")
...
Change-Id: I6964e6731ed461ca3a8c4afde0ddfe48e0105627
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/252620
Reviewed-by: Doug Anderson <dianders@google.com>
Tested-by: Doug Anderson <dianders@google.com>
This config should be opened since the config used for chromeos.
Change-Id: I52dd22b1c1a707e6d27311337a5be6f0041cb7f9
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
We need to declare that we enable all NOCs which are critical clocks
always and clearly and explicitly show that we have enabled them at
clk_summary.
Change-Id: I859664692b4d1bb0dda0ee38295dfcbc3cc70019
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
On the moment, the gt9xx touchscreen driver can't work on chromeos.
Since the driver report event has *not* judge correct by the chromeos.
We need report the singel point touch information for event firstly,
otherwise the chromeos will force a signel point to work.
That's seem a chromeos issue/leak.
Anyway, we can report the point including the signal information
to workaround.
Verify on rk3399evb board with chromeos.
root@localhost / # evtest
No device specified, trying to scan all of /dev/input/event*
Available devices:
/dev/input/event0: goodix-ts
/dev/input/event1: rk29-keypad
Select the device event number [0-1]: 0
Input driver version is 1.0.1
Input device ID: bus 0x18 vendor 0xdead product 0xbeef version 0x28bb
Input device name: "goodix-ts"
Supported events:
Event type 0 (EV_SYN)
Event type 1 (EV_KEY)
Event code 330 (BTN_TOUCH)
Event type 3 (EV_ABS)
Event code 0 (ABS_X)
...
Event: time 1450321044.293221, type 3 (EV_ABS), code 57 (ABS_MT_TRACKING_ID), value 0
Event: time 1450321044.293221, type 3 (EV_ABS), code 53 (ABS_MT_POSITION_X), value 4095
Event: time 1450321044.293221, type 3 (EV_ABS), code 54 (ABS_MT_POSITION_Y), value 4083
Event: time 1450321044.293221, type 3 (EV_ABS), code 48 (ABS_MT_TOUCH_MAJOR), value 8
Event: time 1450321044.293221, type 3 (EV_ABS), code 50 (ABS_MT_WIDTH_MAJOR), value 8
Event: time 1450321044.293221, -------------- SYN_REPORT ------------
Event: time 1450321044.384655, type 3 (EV_ABS), code 57 (ABS_MT_TRACKING_ID), value -1
Event: time 1450321044.384655, -------------- SYN_REPORT ------------
Change-Id: Ic41327a673632e471429ded35b68eecbbd7f3069
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Remove CONFIG_IEP and CONFIG_RK_VCODEC definition for
they aren't required in rockchip chromeos.
Change-Id: I3a0bce0943931a7546378fb7c7e663e1317b93da
Signed-off-by: alpha lin <alpha.lin@rock-chips.com>
When CONFIG_RK_IOMMU disabled, iep build will throw out error
information for some mismatch definitions.
Change-Id: I0fb22550eaaebd62523d794e45de7b94fae8db63
Signed-off-by: alpha lin <alpha.lin@rock-chips.com>
There is a phy config clock in RK3399, it must be control by mipi
driver.
Change-Id: I5c029b79ae5867b652ab761dc7416f78f8e070d2
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Thers is a phy config clock in RK3399, it must be enable before phy
init, and be disable after phy init.
Change-Id: Idb2d4c85f5284065c3f1d540d9e2fddf5565040d
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
fix warning:
warning: format '%x' expects argument of type 'unsigned int',
but argument 2 has type 'size_t'
Change-Id: Ifab0d16f0229aa3d5fc244678298fa2138bd4aa1
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
The vopb/vopl switch register of rk3399 mipi is different from rk3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.
Change-Id: I54542752dddd1b28fc0500c0a763f14c29fe98f0
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Fix a typo making the sclk_i2c4 and sclk_i2c8 access a
wrong register bit offset to handle its gate.
Change-Id: I836244b8e14aa34ef44241c8ff24ebd6b63ed23a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
In current of-thermal, the .set_trip_temp only support to
set trip_temp for SW. But some sensors support to set
trip_temp on hardware, so that can trigger interrupt,
shutdown or any other events.
This patch adds .set_trip_temp() callback in
thermal_zone_of_device_ops{}, so that the sensor device can
use it to set trip_temp on hardware.
Change-Id: I879ea144a9ac21a5032dd885118887b4942c96cf
Signed-off-by: Wei Ni <wni@nvidia.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(cherry picked from git.kernel.org next/linux-next.git master
commit 60f9ce3ada53498409d51da06502392884933f89)
Add resource managed version of thermal_zone_of_sensor_register() and
thermal_zone_of_sensor_unregister().
This helps in reducing the code size in error path, remove of
driver remove callbacks and making proper sequence for deallocations.
Change-Id: Ie2e47805f398ff7b4f1dcc71e0581221d79ba9d2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(cherry picked from git.kernel.org next/linux-next.git master
commit e498b4984d)
The gt9xx touchscreen should be used by rk3399 evb board.
The rk3399-monkey.dtsi and rk3399-chrome.dtsi just run the different OS.
So... we should move the touchscreen node into the rk3399-tb.dtsi.
Change-Id: Ida8203e045e0fc0eb49e8a37e4ad609c230e040f
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The gru/kevin board works the iodomain with gpio regulator.
That's useful for rk3399 kevin/gru board.
Change-Id: I70b6185e3a21a038347b9f8ccd679908817184dd
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Technically emerging the kernel with USE=kgdb is supposed to get most of
this. ...and the kernel command line is supposed to come from
elsewhere. Until we get that happier, maybe this CL is useful.
Change-Id: Idd0100b623eb88b4a4a26922754b71f5cbcd602a
Signed-off-by: Douglas Anderson <dianders@chromium.org>
It's useful. Might be something we can leave on even in a real kernel.
We'll have to see. We have common clock debugging...
Change-Id: I3c1cb55b067a4c54bb425d23664c5f1474016c92
Signed-off-by: Douglas Anderson <dianders@chromium.org>
This patch is learn from Marek Szyprowski's patch:
(drm/exynos: rewrite IOMMU support code)
The patch replaces usage of ARM-specific IOMMU/DMA-mapping related calls
with new generic code for managing DMA-IOMMU integration layer. It also
removes all the hacks, which were needed to configure common DMA/IO address
space on the virtual rockchip-drm device.
Change-Id: I5d2b90002bf135a72ce30cc8503a7d06769835f3
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
There are two VOP in rk3399 chip, respectively VOP_BIG and VOP_LIT.
most registers layout of this two vop is same, their framework arm both
VOP_FULL, the Major differences of this two is that:
VOP_BIG max output resolution is 4096x2160.
VOP_LIT max output resolution is 2560x1600
VOP_BIG support four windows.
VOP_LIT only support two windows.
RK3399 vop register layout is similar with rk3288, so some feature can reuse
with rk3288.
Change-Id: I76f94c93b0e63e4fbba51755e92c604211613e8b
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
This initial patch adds to support the gru/kevin board for rk3399 SoCs.
It builds at least:
make -j32 ARCH=arm64 CROSS_COMPILE=aarch64-cros-linux-gnu- dtbs
Change-Id: I7f3841513da130c107aca0d6b393b2bf269a5396
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Add devicetree bindings for i2s controller found on rk3399
processors from rockchip.
It's helpful to add full set of compatible strings for serials
of Rockchip SoCs (rk3066, rk3188, rk3288, rk3399).
Change-Id: Ida3f9ffecda52d81016bdb6edb640568ed8c872a
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 255edcdfab)
there maybe more than one i2s module inside chip, and these i2s modules
have different channels features.
for example: there are 3 i2s in rk3066, one support 8 channels playback
and 2 channels capture, but the others only support 2 channels playback
and 2 channels capture.
in order to compatible with these various chips, we add playback and
capture property to specify these values.
there are default channels configuration in driver: 8 channels playback
and 2 channels capture. if not add property, we use the default values.
Change-Id: I45f3214160877223ba9722bd38a36584e416b14d
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit c4f9374ddc)
This patch sets the dividers autonomously.
when i2s works on master mode, and sample rates changed. We need to change
bclk and lrck at the same time for cpu internal side.
As the input source clock to the module is MCLK_I2S,
and by the divider of the module, the clock generator generates
SCLK and LRCK to transmitter and receiver.
Change-Id: I377f0f08656659787b980785fab0b69197b7b80b
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 2458c37779)
This patch like below:
----
commit 3860aa1ccf
Author: Heiko Stuebner <heiko@sntech.de>
Date: Sat Jan 9 03:18:51 2016 +0100
ARM: dts: rockchip: swap i2s clock ordering on rk3036
For sound setups using the simple-card mechanism, the main clock
(sysclk) is expected to be the first element. For the i2s-driver
itself it doesn't matter, as it uses named clocks, so we can just
swap them.
----
If we set HCLK_I2Sx at first, rockchip_i2s_set_sysclk will set the
HCLK_I2S freq (from example is 100MHz) to set the i2s_div, it is
incorrect.
Change-Id: Iab69d541c47d1293a784ebffc23f6c1ceaf9c0b1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We need to take care of the vop status when use rockchip_drm_crtc_mode_config,
if vop is disabled, the function would failed, that is terrible.
Save connector type and output mode on drm_display_mode->private_flags on
connector mode_fixup, then we can configure the type and mode safely
on crtc mode_set.
Change-Id: I129cf8a2f100fc19fe96f1d8985e905bea477e28
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
This patch like below:
----
commit 3860aa1ccf
Author: Heiko Stuebner <heiko@sntech.de>
Date: Sat Jan 9 03:18:51 2016 +0100
ARM: dts: rockchip: swap i2s clock ordering on rk3036
For sound setups using the simple-card mechanism, the main clock
(sysclk) is expected to be the first element. For the i2s-driver
itself it doesn't matter, as it uses named clocks, so we can just
swap them.
----
If we set HCLK_I2Sx at first, rockchip_i2s_set_sysclk will set the
HCLK_I2S freq (from example is 100MHz) to set the i2s_div, it is
incorrect.
Change-Id: I2b424ded3845b8ccd3ef233e43c5f9f915544547
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
