optimize opp table for the chips with different leakage.
Change-Id: Id7a64148aa537b4cbbec07962044c37c582f59df
Signed-off-by: Liang Chen <cl@rock-chips.com>
The oem zone ranges from 256 to 511 bytes. userspace
can read/write the raw NVMEM file located at
/sys/bus/nvmem/devices/rockchip-otp0/nvmem
The rest of otp which ranging from 0 to 255 bytes is
used for system, it is protected by hardware, any writes
to this range will be ignored and not take effect.
e.g.
/#hexdump -C /sys/bus/nvmem/devices/rockchip-otp0/nvmem
00000000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*
00000100 ff ff ff ff ff ff ff ff 0f 0f 0f 0f 0f 0f 0f 0f
00000110 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
00000120 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*
00000200
Change-Id: I3e222d87525887fd5a38aa724e97f2dd163345aa
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Add the clock tree definition for the new RK3568 SoC.
Change-Id: I9c2282938ec51ddf2dd71390b9b0cfef1f0d2735
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add the dt-bindings header for the rk3568, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3568.
Change-Id: I93d9da3625d4f92c263013e850885576be646e2c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.
Change-Id: I1b9a76a6c3edf28c466493a7b72765e55ba304fc
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
to optimize reading and writing of ddr, aliged with 256,
sync with virtual width
Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
Change-Id: I5cb7e3a08e8805371eeac30cd992f97a0c759076
If aclk_gmac is not set, the default configuration
is 98.304M, which cause the tcp checksum error.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I7009541f6a035285d038f84d7a4222aba26beed0
this patch add HDR_X2 mode support and
update gain settings from vendor
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: Ibddb6ac2cf0d2529bae2242e9076f6a6dd6ebe33
Keep 0dB for adc/dac volume, and using hardware loopback
which is dac_l+adc_r.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: Ie226791c5bd62324552237d98cc10b6bf31ac5b5
This patch add adc-volume/dac-volume/aec-mode and be easy to
configure some simple functions without alsa-utils.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: Ic58188a0ef72fe5236b523445dc530e649a0e248
This patch fix this error:
[ 0.755533] es8311 4-0018: ASoC: no dapm match for DMIC MUX --> FROM ADC OUT --> SDP OUT MUX
[ 0.755613] es8311 4-0018: ASoC: Failed to add route DMIC MUX -> FROM ADC OUT -> SDP OUT MUX
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: I6032e9f81a79ac04ceaba590658cdfd9e539b84a
This patch adds support for rockchip codec digital interface,
which is used to communicate with external codec analog part
with pdm link.
Change-Id: I9ea7020d904b63f7a34696b0f538accd8c700076
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
It's mainly composed of digital ADC and digital DAC. The digital ADC
converts PDM data into PCM data and then sends them out through I2S.
The digital DAC receives PCM data from I2S and then converts them into
PDM data.
Change-Id: I46533228b67c127e6fa70d45d4152763fa7290e0
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
The UBIFS file system does not need misc partition,
So modify the mtd of rootfs to 2.
Change-Id: I7f74cace5963dc0b5aafc6da6ab16a1a520b0257
Signed-off-by: Mark Huang <huangjc@rock-chips.com>
Make the hclk_mmc is available before accessing the registers.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I2ab1556eb2376c77d8e05a66eb64cb367c7919d3
For linear calculation, code needs to be converted to Int,
otherwise the calculated value may overflow at ultra-low temperature.
Change-Id: I64c45b1f5ebc86da853180ca7bb3cb83234f2a64
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Split the hpd gpio handling from the host irq handler.
Change-Id: I0d62201095ab82f5ed0ddcfd53abaef6089a2e9d
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
