1. add delay in setting to fix probability reg write failed
2. remove duplicate global register setting.
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: I8381c9b03480de4119abe225e1ef561a51dec59b
For rockchip sdhci controllers, SDHCI_RESET_ALL resets also CQHCI registers.
Normally, SDHCI_RESET_ALL is not used while CQHCI is enabled, but that can
happen on the error path. e.g. if mmc_cqe_recovery() fails, mmc_blk_reset()
is called which, for a eMMC that does not support HW Reset, will cycle the
bus power and the driver will perform SDHCI_RESET_ALL.
So whenever performing SDHCI_RESET_ALL ensure CQHCI is deactivated.
That will force the driver to reinitialize CQHCI when it is next used.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Iee491501ff7e32e347303f5389f22eef9f8f658b
The dapm power sequences is
static int dapm_up_seq[] = {
[snd_soc_dapm_supply] = 3,
[snd_soc_dapm_dac] = 8,
[snd_soc_dapm_hp] = 12,
[snd_soc_dapm_spk] = 12,
};
static int dapm_down_seq[] = {
[snd_soc_dapm_hp] = 4,
[snd_soc_dapm_spk] = 4,
[snd_soc_dapm_dac] = 7,
[snd_soc_dapm_supply] = 13,
};
We should enable PA power after dac on and disable before dac off
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
Change-Id: Ie5b7d5736496061e8f7551bf7d40ffba83015144
ROCKCHIP_VOP2_PHY_ID_INVALID has a value of -1 that is out of range
for vop2_layer_name_list. Convert it to "INVALID".
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Change-Id: I0aaa36c5a51ef0227847567ca1b495d16470ee1b
The detailed changes as follows:
1.Add flag max_bpc and format_yuv to check whether the
platform support 10 bit per component and YUV444/YUV422.
2.Add exact bpp related to output format in bandwidth
calculation, which is fixed to 24 before the patch.
3.Add .atomic_get_input_bus_fmts() and .atomic_get_output_bus_fmts()
to get the supported input and output bus formats.
Change-Id: I78ef43d19b3a2970a961b0f668a75ef857951dfe
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
1. Disable auto_rst to avoid false interrupt generation.
2. Reset core_clk before startup to avoid hardware runaway due to
continuous scaling.
3. Configure auto_clean command count to avoid iommu access exception
after command count from 4095->0.
Update driver version to 1.3.4
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I12f312280429996c182952fbe8c8c4a20155dc4f
VERSION >= SAI_VER_2311
Support Frame Sync xN (FSXN)
Support Frame Sync Error Detect (FSE)
Support Frame Sync Lost Detect (FSLOST)
Support Force Clear (FCR)
Support SAIn-Chained (e.g. SAI0-CLK-DATA + SAI3-DATA +...)
Support Transmit Auto Gate Mode
Support Timing Shift Left for TX
Optimize SCLK/FSYNC Timing Alignment
VERSION >= SAI_VER_2403
Support Loopback LR Select (e.g. L:MIC R:LP)
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I9c957b5115686df2573a06b9276f26a15e709d4e
This patch converts the original unreadable machine log output into
human readable data.
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Change-Id: Ibec0a11d8f65c58b0ba0c5c5bc3daa5bc5c9ca81
Notify the usb role to usb2 phy when we received role_switch set from
the TCPM (Type-C Port Manager) to escape BC1.2 charge detection at host
mode in usb2 phy driver.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Id41df3d25b29771d4461cfd1106ca3f3c2572a18
TX_CTL and RX_CTL MSB bit is in different bit filed.
Change-Id: I79ada641acd2034998400e2b2f7310cbe1d5de3c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Since the speed requirement, this adds another txpoll-period time
in microseconds support.
The feature depends on CONFIG_MAILBOX_POLL_PERIOD_US is selected.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Iffc098e80c378f1b16d54135e9b930f57d841a6d
Select CONFIG_MAILBOX_POLL_PERIOD_US to use microseconds resolution
for txdone_hrtimer polling to increase TX speed.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Icd76dc79fc8d9cb02b7c12837b8b344e31941050
This commit updates the rk3562_robot.config to ensure compatibility with
kernel version 6.1
Steps performed:
1. Generate the default configuration:
make ARCH=arm64 rockchip_linux_defconfig
2. Backup the old configuration:
cp .config .config-old
3. Apply the rk3562_robot.config:
make ARCH=arm64 rockchip_linux_defconfig rk3562_robot.config
4. Backup the new configuration:
cp .config .config-new
5. Generate the diff and update the rk3562_robot.config:
./scripts/diffconfig -m .config-old .config-new > arch/arm64/configs/rk3562_robot.config
Change-Id: Ib02eb95158b02547147c43c533dcb5f22753b149
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Bus devfreq policy support a group of bus clks drive DVFS together with
a single regulator.
Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: I920a7df009638041b6b6cf2b77f914b6efc7862d
Add bindings for the Rockchip Flexbus QPI serial flash controller.
Change-Id: I9a4126e14cd732cb5daa4b6b685678758584389a
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
