Commit Graph

1060941 Commits

Author SHA1 Message Date
David Wu
5cfc724687 i2c: rk3x: Add auto support for rockchip
If the transfer finished, auto stop to end this transfer.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I23cd39e63b8ce292a63c9530edde2c9b72c289cb
2021-11-18 14:37:58 +08:00
Zefa Chen
3c60ce2725 media: move rk_vcm_head.h from drivers/media/i2c/ to include/uapi/linux/
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I1774f05820df31468db8df196dccc7475730b1b5
2021-11-18 14:24:25 +08:00
Zefa Chen
6b8539ff7c media: i2c: imx464: support get/set sync mode
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I6eecbffed42f747e7622f66f450762a461f83b3b
2021-11-18 14:21:59 +08:00
Zefa Chen
d79447a5e8 media: rockchip: rkcif support RKCIF_MASTER_MASTER/RKCIF_MASTER_SLAVE sync mode
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I71270f1e0e3ba309683092f1ae1d01122bc4b613
2021-11-18 14:18:54 +08:00
Zefa Chen
08b6f9fdcf media: rockchip: cif: mipi csi host write fs/fe code
to avoid error match fs/fe

Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: Ib2097f0274b66cf750ada07f34b36e503e813ef6
2021-11-18 14:18:08 +08:00
Ding Wei
25da6d8173 video: rockchip: mpp: Move kthread from device to queue
reason:
    if device combo, the device are share the same queue,
    which hardware run in different time. thus, these can
    also use the same kthread.

Change-Id: I92f6ec4d753b223b55923ae3a243144ba65dc47e
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
2021-11-18 14:17:01 +08:00
Shunqing Chen
f6420d7bf5 arm64: dts: rockchip: enable bq25703 and cw2015 for rk3588s tablet
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Change-Id: I1699d2a82fbea8b2929e88f5f91931b1e291409d
2021-11-18 14:16:28 +08:00
Tao Huang
24770f7580 arm64: rockchip_defconfig: Disable CONFIG_ZONE_DMA
According to gki commit 17f9730086 ("ANDROID: GKI: Disable CONFIG_ZONE_DMA on arm64").

After 1a8e1cef76 "arm64: use both ZONE_DMA and ZONE_DMA32" ZONE_DMA
gets enabled by default. Disable this config to remove unused zone.

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I555747b4a3aaccb914c7ce2895f08504d2b2dcc2
2021-11-18 11:37:30 +08:00
Jianqun Xu
9f19c0d417 arm64: dts: rockchip: rk3588s-pinctrl fix mipi camera clks
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Id33754b3c8dea5c36f0f84e49df4606f547077d8
2021-11-18 10:07:02 +08:00
Shunqing Chen
1c21a1cc6b power: supply: cw2015: support dual cell
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Change-Id: I77af842e4b020a59eaa8d825c0d7dd6977fabc76
2021-11-18 09:35:45 +08:00
Zefa Chen
8ea7125efd arm64: dts: rockchip: fixed vicap address size for rk3588
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I0e3023b8b4707412f07c41c6092f6d7be0766939
2021-11-18 09:34:50 +08:00
Jon Lin
f6ec516777 mtd: spinand: foresee: Add support for F35SQA002G
Support F35SQA002G

Change-Id: Ia5e695893e9a961645592da127cef7b7419355a7
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2021-11-18 09:33:26 +08:00
Cai YiWei
588b499315 media: rockchip: isp: fix fbc iommu err with multi device case
Change-Id: I2da80020ea4e08a906586fd46ef7f3c92159d0a8
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
2021-11-18 09:29:21 +08:00
Cai YiWei
5693340003 media: rockchip: isp: isp3 max clk to 702M
Change-Id: I122b9c5c0d11d62c0eb0800028be24c2e4cb7538
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
2021-11-18 09:29:21 +08:00
Elaine Zhang
da0404e65c arm64: dts: rockchip: rk3588: add more clks for pd nodes
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ia305f945286c5489b9696cbc7df181e046392b6b
2021-11-17 20:07:25 +08:00
Elaine Zhang
83922fcb65 clk: rockchip: rk3588: fix up some clk parents for clk-link
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Id88179e2a852caf822f61cf79d73a4b6bbe3f893
2021-11-17 19:56:03 +08:00
Elaine Zhang
2478213d05 arm64: dts: rockchip: rk3588: add dts nodes for special clocks that use clk-link
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I2d1aadc838295a5452812cc7a299e3d09a3dd8a2
2021-11-17 19:56:03 +08:00
Elaine Zhang
5b5186d6fe clk: rockchip: link: update the link driver for rk3588
remove unnecessary clk link.
add rkvdec clk link.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I8119d8ca31c5c00375dcd85f5142642e9e304675
2021-11-17 19:56:02 +08:00
Lin Jinhan
6735100951 hwrng: rockchip: make the function name more accurate
Modify rk_rng_v1_read to rk_crypto_v1_read.
Modify rk_rng_v2_read to rk_crypto_v2_read.

Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I0cb094ef7c3cc6915832411e995ffbf0d0d0fbfa
2021-11-17 19:29:48 +08:00
Lin Jinhan
9c057f7652 dt-bindings: rng: Document the Rockchip TRNG V1 HW RNG bindings
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I3c70e5df2d7495edd5299f0283fc2bb934569a6b
2021-11-17 19:29:14 +08:00
Lin Jinhan
5c7f3b2116 hwrng: rockchip: move power management into rk_rng_read
There are two copies of the same power management code
 in rk_rng_v1_read and rk_rng_v2_read, moved to rk_rng_read.

Change-Id: I104cf22a8093213a6d22f7a723d3cfaf36aa4414
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
2021-11-17 19:27:42 +08:00
Lin Jinhan
8f3ec33049 arm64: dts: rockchip: rk3588s: rng: use scmi_clk
rng module should use scmi_clk rather than cru.

Fixes: b56b10f007 ("arm64: dts: rockchip: rk3588s: add rng node")
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I49994529fcc209c2bc173c1abc497536fb920302
2021-11-17 19:26:49 +08:00
Frank Wang
94dab507e0 usb: typec: fusb302: fix i_comp and i_bc_lvl interrupt
The software utilizes I_COMP and I_BC_LVL interrupts to determine an
attach and what type of port is attached. and I_COMP interrupt also
alerts software that a SRC detach has occurred. So unmask I_COMP for
SRC and I_BC_LVL for SNK.

Fixes: 48242e3053 ("usb: typec: fusb302: Revert "Resolve fixed power role contract setup")
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Ib4cf3b752d0db116f2603d5e1f3ee5c7d114714a
2021-11-17 18:47:51 +08:00
Sugar Zhang
0909f637bb clk: rockchip: rk3588: Fix digital-fracdiv signoff freq
All the digital-fracdiv signoff freq are the same, and up
to 1.5G on rk3588.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Id4b6b43c05b256a2b77d3c6c0603953b7340eca0
2021-11-17 18:39:40 +08:00
Sandy Huang
67a4a699aa drm/rockchip: vop2: update dsc config
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Id02ab53b59997e8a06dd8bcc1b8c158ca35c5595
2021-11-17 18:23:20 +08:00
Huang zhibao
da37a53ade arm64: dts: rockchip: rk3588-nvr-demo: add dp2vga support
Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: I68b6ae2d22c8b57003b3fab1cfeb811c792bd506
2021-11-17 18:18:17 +08:00
Sandy Huang
7a2e062e38 drm/rockchip: dsi2: init dsc info for dual channel mode
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ia67d7f57ff344cb9273458375209b576e5b4940d
2021-11-17 18:17:50 +08:00
Shawn Lin
151189f520 arm64: dts: rockchip: rk3588: Set SDHCI core clk to 200MHz
As we mask our SDHCI controller as SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
host->max_clk is derived from core clock in the first place. Then
f_max works together with it.

If we adjust loader's core clk setting, such as 50MHz, we will get
50MHz for host->max_clk, because .get_max_clock() reads core clk
when probing driver. That will lead f_max be set to 50MHz as well,
no matter if max-frequency is set higher than 50MHz.

We can simple solve this problem by assigning core clk as 200MHz
in the first place and then let max-frequency property takes over
it.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I25986720fa441da3786ca0904a2d4b1a5b0568e5
2021-11-17 18:13:16 +08:00
Yifeng Zhao
d6e5a46807 arm64: dts: rockchip: enable hs400 for rk3588 evbs
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ida8f8f6e355f158b2c6552e130b98a9526543d9d
2021-11-17 18:11:46 +08:00
Yifeng Zhao
ba5f874356 mmc: sdhci-of-dwcmshc: enable HS400 for rk3588
1. set CARD_IS_EMMC bit to enable Data Strobe for HS400
2. config the transmit clock source (DLL TX) is original clock input
3. config Command output source and Command output enable are from
register output triggered by clock falling edge

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I5b34fecde7bb1d05211c7d9c42f54c8e154d367e
2021-11-17 18:11:21 +08:00
Algea Cao
b73433e36e drm/rockchip: Add dw-hdmi-qp driver
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I6ac976dc3693bfdac1ac09570f2c4d0efb87fe9e
2021-11-17 18:01:49 +08:00
Algea Cao
691a8a86be arm64: rockchip_defconfig: enable CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I042d351a9adfee66b4c0cf2c05cde625bdc1e62a
2021-11-17 18:01:35 +08:00
Algea Cao
b4fa0a1a58 phy/rockchip: Add Samsung HDMI/DP Combo PHY HDMI driver
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I706f2c309e2553316957190d44c47f426a1f2594
2021-11-17 18:01:35 +08:00
Zhen Chen
583d67f999 MALI: bifrost: rk: add definition and implementation of CLK_RATE_TRACE_OPS
Picked from ./platform/devicetree/.

This makes GPU utilisation info available and resolve the warning log below:
[   19.641700][   T83] WARNING: CPU: 0 PID: 83 at drivers/gpu/arm/bifrost/csf/ipa_control/mali_kbase_csf_ipa_control.c:239 kbase_ipa_control_handle_gpu_power_off+0x128/0x198

Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
Change-Id: I7ce8d0f52d6340659b2c9ca9692c48043e1060c1
2021-11-17 17:00:34 +08:00
Huang zhibao
c61bb449b9 arm64: rockchip_linux_defconfig: Enable CONFIG_PHY_ROCKCHIP_USBDP
Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: I42fc00960d75ee0e45853d7b8d25451d95dfe532
2021-11-17 17:00:15 +08:00
Huang zhibao
b66c6faa49 arm64: rockchip_linux_defconfig: enable CONFIG_ROCKCHIP_DW_DP
Enable the DP driver used on Rockchip RK3588 SoC.

Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: I4d645edebf90ceaa35b52b0ccf029c17d1a51e67
2021-11-17 17:00:00 +08:00
Jianqun Xu
48ce88b1b5 arm64: dts: rockchip: fix rk3588s to use tsadc_shut iomux
To use tsadc_shut function, tsadc must switch to cru_shut_mode,
because tsadc_shut signal have to go through the cru to get to
tsadc_shut signal.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I9bc816db35bdf1c107db4e301d9f3353cb651dcf
2021-11-17 16:15:44 +08:00
Huang zhibao
799f5e763c arm64: dts: rockchip: rk3588-nvr-demo: fix pcie3.0 reset io
Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: I12030801ef502af553239702e06f52ac18f39e8e
2021-11-17 16:14:32 +08:00
Dongbo Yang
0b27ae1db5 misc: add driver for rk803.
Signed-off-by: Dongbo Yang <db.yang@rock-chips.com>
Change-Id: Ieba56551c48ed42f7f24c631b117d40a6e14a8f4
2021-11-17 16:14:04 +08:00
Kever Yang
a3a5483632 arm64: dts: rockchip: rk3588-evb: Add pcie3-phymode setting
rk3588 boards may have different pcie3-phymode, default as below id not
set:
rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: If158eb47f679d0c7b184b6bd64262d0f764b97f3
2021-11-17 16:08:30 +08:00
Kever Yang
70c3026b5f arm64: dts: rockchip: rk3588: Include phy-snps-pcie3.h
rk3588 boards may have different pcie3-phymode.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I76825c09014481a06af4c04d0b9b1cc0fee89a8d
2021-11-17 16:08:30 +08:00
Huang zhibao
1bae377ec6 arm64: dts: rockchip: rk3588-nvr-demo: add regulator-init-microvolt
Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: I5edd9b064f08e6249654678826cadb00caa75deb
2021-11-17 16:08:30 +08:00
Mark Huang
09a6f92f07 arm64: dts: rockchip: rk3588-nvr: enable gpu
Signed-off-by: Mark Huang <huangjc@rock-chips.com>
Change-Id: I0e6f97011882db50feb45b5794706bdcf2cdfe94
2021-11-17 14:16:14 +08:00
Frank Wang
b1368b8774 arm64: dts: rk3588: revert peripheral dr_mode for usbotg0
Restore usbotg0 dr_mode to "otg" that Type-C controller can switch the
mode via "role_switch" callback for RK3588 EVB1, EVB3 and EVB4.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I6e7d83acb468d50e31ffdfdee6adcd7c5330d776
2021-11-17 14:15:43 +08:00
Simon Xue
400193dc28 arm64: rockchip_defconfig: Enable CONFIG_ARM_SMMU_V3
There are two MMU600 instances in RK3588.

Change-Id: Iec54e5a9135bbdda01b0bcbe6681cee22ff775ac
Signed-off-by: Simon Xue <xxm@rock-chips.com>
2021-11-17 11:51:15 +08:00
Guochun Huang
42d1582e64 drm/panel: simple: fix unexpected pps packet sending
use helper functions to send dsi picture parameter set data
type packets, the size of struct drm_dsc_picture_parameter_set
is 128 bytes, it may be greater than the size of pps panel required,
so the redundant part should default to zero.

Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I8b937b052cc0d579dd78859ef1aa04aea818d694
2021-11-17 11:22:04 +08:00
Wyon Bi
29d3f8c8b9 drm/rockchip: dw-dp: Fix audio infoframe buffer offset
drivers/gpu/drm/rockchip/dw-dp.c:1911 dw_dp_audio_infoframe_send()
error: hdmi_audio_infoframe_pack() '&buffer[4]' too small (26 vs 30)

Fixes: 9548fbb10c ("drm/rockchip: Add support for Synopsys DesignWare Cores DPTX")
Change-Id: I34142ae76b428c4ada3debfe80698af63ffd8f1f
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2021-11-17 11:17:56 +08:00
Shunhua Lan
ec1a0d929d ASoC: es8323: enable route config
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
Change-Id: Ia18a01afbd72195871d847ee3a17e7a7f9dca1c2
2021-11-17 11:16:54 +08:00
Sugar Zhang
72c304699f clk: rockchip: rk3588: Add audio fracpll freq
983040000 for SR:
  8k, 16k, 24k, 48k, 96k, 192k

903168000 for SR:
  11.025k 22.05k, 44.1k, 88.2k, 176.4k

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ibd4ab8e18cfc1e973d62b920084cfbe8d3000b0d
2021-11-17 09:37:15 +08:00
Shawn Lin
ee99fe07a7 PCIe: rockchip: Add more legacy int support
Some vendor drivers rely on flow control by toggling
enable/disable virtual irq if using legacy interrupt.
It can certainly change the behaviour by function
drivers, but adding corresponding operations would make
RC driver more flexible.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Idf3e6a0ca9c4ebde369745713a88db53e3f72ea5
2021-11-16 21:42:05 +08:00