When 4K x 2k 60Hz/50Hz tmds clock is above the max tmds clock, setting its
color to YUV420. A few TV edid declare that they can't support
4K x 2k 60Hz/50Hz YUV420, we still set color to YUV420 or 4K x 2k 60Hz/50Hz
tmds clock will over the limit.
Change-Id: Id57c9313ab52973927c578d0eb2a7b1b30cb9ec1
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
First, write hdcp key by "ProvisioningTool" if you want to
enable hdcp function, or else will auth fail.
To check whether the hdcp is enable or not
#cat /sys/class/misc/hdmi_hdcp1x/enable
0:hdcp is disabled
1:hdcp is enabled, hdmi screen will be pink if it is failed;
2:hdcp is enabled, hdmi screen will be normal if it is failed;
Enable or disable hdcp function
#echo 0 > /sys/class/misc/hdmi_hdcp1x/enable
#echo 1 > /sys/class/misc/hdmi_hdcp1x/enable
#echo 2 > /sys/class/misc/hdmi_hdcp1x/enable
Get the status of hdcp
#cat /sys/class/misc/hdmi_hdcp1x/status
The result will be one of the follow list:
hdcp disable;
hdcp_auth_start
hdcp_auth_success;
hdcp_auth_fail;
unknown status.
Change-Id: Iac6c7d6a1196ce9cf2869d7916bbe6c8941ec13b
Signed-off-by: Huicong Xu <xhc@rock-chips.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Hdmi suspend or resume may be called before hdmi initialization. We must
verify that hdmi is initialized first.
Change-Id: I2a680209e64b9c1aebc2d9ee19d543927137afd0
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
If HDMI HPD detect delayed work won't be cancel, system will
crush because clk and PD has been disabled. So HDMI HPD detect
workqueue should be flushed when system suspend.
Change-Id: Idb8018c2efcffc3aee5fd80872f1270360809235
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
If edid can't be got when hdmi plug in, hdmi color depth mask and format
won't be updated. The color list in the setting are those of the previous
TV. This commit fix the error.
Change-Id: I5ed4be5efa2a69be0b58489f58a3af5de9912292
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
According to HDMI 1.4b specification: If the transmitted video
format has timing such that the phase of the first pixel of
every Video Data Period corresponds to pixel packing phase 0
(e.g. 10P0, 12P0, 16P0), the Source may set the Default_Phase
bit in the GCP. The Sink may use this bit to optimize its filtering
or handling of the PP field.
This means that for 10-bit mode the Htotal must be dividable by 4;
for 12-bit mode, the Htotal must be divisible by 2.
Change-Id: I02e632d095141cbabcba06dc1321ae0dc69dc736
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
When the color depth is 24 bits per pixel video, the CD
field in General Control Packet should be "Color Depth
not indicated", then the colordepth in register vp_pr_cd
& csc_scale should assign to zero.
BUG=chrome-os-partner:38212
TEST=speedy board, Test with Agilent Technologies U4002A
HDMI Protocal Analyzer
Change-Id: Ifd5767d339fdbff11e234ec0891c8f3df1dd66a5
Reviewed-on: https://chromium-review.googlesource.com/261850
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Yakir Yang <ykk@rock-chips.com>
Commit-Queue: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Formula3 and Formula2 for csc decimation will cause hdmi yuv422
display err.
Formula3:
The pixel color of left 0-14 columns and right 0-12 columns is
err.
Formula2:
The pixel color of left 0-2 columns is err.
Change-Id: I94fdd5fd962a24fde02dde1fe3ac10437ad117ad
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Under following processes, rxsense will be not match the real
signal status.
1. HDMI plug in, irq is triggered.
2. HDMI irq is mute in dw_hdmi_hardirq, bring up dw_hdmi_irq.
3. For HDMI connection is not stable, phy_stat read in
dw_hdmi_irq may be zero, then hdmi->rxsense will be false.
4. Connection fallback to stable, but dw_hdmi_irq had not
unmute the irq, irq is not triggered again, and hdmi->rxsense
keep false.
5. repo_hpd_event inform HDMI is pluggned in, dw_hdmi_bridge_enable
is called to enable HDMI. For rxsense is flase, bridge is not
powered up.
When repo_hpd_event is called, we think HDMI connection is stable,
updating rxsense is reliable.
Change-Id: Ie1f52f65b15e9a603dad9200529202053528a390
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Introduce status node in debugfs to show HDMI output status,
such as phy status, color and eotf.
Here is a sample log:
PHY enabled Mode: HDMI
Pixel Clk: 594000000Hz TMDS Clk: 594000000Hz
Color Format: YUV422 Color Depth: 10 bit
Colorimetry: ITU.BT2020 EOTF: ST2084
x0: 0 y0: 0
x1: 0 y1: 0
x2: 0 y2: 0
white x: 0 white y: 0
max lum: 0 min lum: 0
max cll: 0 max fall: 0
Change-Id: I5d458b633dd3bd9aab67cc91f1695621937e58f5
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This reverts commit 384134cb60.
bcm2079x is unused.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ibbc1b18fbadc1de9fa66915348b3382533ad1621
For compatibility with GKI, drm_display_mode_from_vic_index() can't
be export function. So we use default mode list when edid can't
be got.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ic7d046e4ccf36981449d36067efd8bb2388e27e4
msgs[0].addr will be 0x30 when read edid with more than 2 block.
but still a read edid operation with write DDC_ADDR to
HDMI_I2CM_SLAVE register.So fix it.
Change-Id: I5f0cd9172acd4a68d5b54eaf99f17b45385a4263
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
To set dw hdmi i2c bus adapter scl clock rate, we introduce two device
tree parameter, ddc-i2c-scl-high-time-ns and ddc-i2c-scl-low-time-ns.
ddc-i2c-scl-high-time-ns: how many ns SCL hold high
ddc-i2c-scl-low-time-ns: how many ns SCL hold low
After measurement, 50KHz scl clock rate recommended configuration is:
&hdmi {
ddc-i2c-scl-high-time-ns = <9625>;
ddc-i2c-scl-low-time-ns = <10000>;
};
100KHz recommended configuration is:
&hdmi {
ddc-i2c-scl-high-time-ns = <4708>;
ddc-i2c-scl-low-time-ns = <4916>;
};
If dts parameter is not available, the default scl rate is 100KHz.
Change-Id: I6f6b0bf1694ab59e70da789ead99e15a53c93e4d
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This patch add hdmi_output_colorimetry to support modify
hdmi output colorimetry. It could be following value:
- None
- IUT_2020
Default value is None, which means normal hdmi output
colorimetry.
Change-Id: Ib4883fd0553d9d4193c7295812d2c1433724fe63
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
there are maximum TMDS clock limit, when the clock is out of range
reducing frequency by set color format to yuv420 and/or set color
depth to 8bit
Change-Id: I8b79de97329561bf0399d05c0264a5c818f844fc
Signed-off-by: Huicong Xu <xhc@rock-chips.com>
If color depth is automatic, it is same as 8bit.
If tmdsclk > max_tmds_clock, fall back to 8bit.
Change-Id: Ia8cbf5206831ef99456ae59add94c6f8b5a33380
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
For some display device, max_tmds_clock is 0, we think
max_tmds_clock is 340MHz. If tmdsclock > max_tmds_clock,
depth should fall back to 8bit. And If display mode support
YCBCR420, output format is YCBCR420.
Because max tmds clk of RK3368 is 340MHz, hdmi output policy
is same as mentioned above.
It is need to check tmds clock rate at the last. So we move
depth checking into dw_hdmi_rockchip_select_output.
Change-Id: I27e029fc0171b175ddbfa453ed12854ab6a7432b
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
HDMI will set vop eotf and color space according to display mode.
Change-Id: I469d03dd1f14a2bcd75ed5c8e3227cd1d34eb354
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
HDR_SOURCE_METADATA property is used to set source hdr metadata,
which will be sent to sink though HDMI DRM infoframe.
Change-Id: If3500cb505c16c2f0caf66b8e64b4d80b93b228f
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
When switch color new hdmi phy config may not be set because hdmi phy
is already on in upstream code.
So we should power down hdmi phy first before power on hdmi phy when
set new hdmi phy config.
Change-Id: Icb1cf29931f1084cc70b0b320137260491497771
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Introduce mtmdsclock to record tmds clock, which is different
to mpixelclock in deep color mode. Use this variable to select
synopsys phy curr_ctrl/phy_config, and audio N/CTS.
Change-Id: Ia78dee9c4901d2f1ca7f339dfb030d65bbf6861d
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Compare the status before and after to determine
whether to enable hdmi phy.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ided938ab83d786d0003afad25a9a191d105d199e
This reverts commit 1b9ac44296.
testcode is unused.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I8b770eb8069289e59352e04081de4963cccc6a89
Both the init_timer() and timer_setup() APIs have been removed. This
script will not be needed any more.
Signed-off-by: Kees Cook <keescook@chromium.org>
(cherry picked from commit 9477b4ad70)
Change-Id: Ifaf91409c5360f5d1f3b24f924f009a28efd56e9
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This reverts commit 8bffe04905.
rk-isp10 is unused.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Iefade8a612b8cb88f3632e4ddea9410d5ece19b9
After commit cdc6f7d0b0 ("media: remove unused video drivers"),
these files are unused, so just remove them.
include/media/camsys_head.h
include/media/v4l2-chip-ident.h
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ib561e90ec55f8f2b51c6d5fe3e03fe25836e511e
Add no-sdio/no-sd for emmc; no-sdio/no-mmc for sdcard; no-sd/no-mmc for
sdio.
Change-Id: I13d3918f41f63ed9b27e9969e6f89d1006c9d45c
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
