add support for rgb panel or rgb covert to other interface panel.
Change-Id: I190ce6e08d38f794ecabb863e0def5e74890f75a
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
There are two clocks between armclk and pll_apll on px30,
but there may be only one clock on some Socs, so it will
get a error pll clock.
Change-Id: I34116a1ec824b884d3745082f3546cd9ab4c0d21
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add constants and callback functions for the dwmac on rk3308 soc.
The base structure is the same, but registers and the bits in
them moved slightly, and add the clk_mac_speed for the select
of mac speed.
Change-Id: Ieaea3ade9e51d5118f0eb855d8e02febfb2275d1
Signed-off-by: David Wu <david.wu@rock-chips.com>
The MMC sample and drv clock for rockchip platforms are derived from
the bus clock output to the MMC/SDIO card. So it should never happens
that the clk rate is zero given it should inherits the clock rate from
its parent. If something goes wrong and makes the clock rate to be zero,
the calculation would be wrong but may still make the mmc tuning process
work luckily. However it makes people harder to debug when the following
data transfer is unstable.
Change-Id: Ifeb4c063cb73e0a444fd8819ef3128256331cd7a
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from https://patchwork.kernel.org/patch/10258071/)
If the mac_refclk is provided from mac controller, the pin of mac_refclk
needs to setup 12ma strength, or the signal is not good.
If the mac_refclk is provided from phy, the pin of mac_refclk needs not
to setup 12ma strength, the phy would do it.
Change-Id: I4f6e6d081b4616363d10358c9e36d71cacbdb134
Signed-off-by: David Wu <david.wu@rock-chips.com>
Opp rate is used to calc power in thermal framework, so we record
this rate instead of real clock rate.
Devfreq is not ready in target() when use performance governor, so
we need record opp rate in probe().
Change-Id: Iec1918ad5d12124b9f112964f247339e0d50645f
Signed-off-by: Liang Chen <cl@rock-chips.com>
400MHz and 600MHz aren't supported at present.
This had submitted in commit a8c497e79d
("arm64: dts: rockchip: rk3328: Disable 400MHz and 600MHz for dmc")
but was modified in commit 59af91b563
("arm64: dts: rockchip: auto select opp-table by leakage for rk3328")
by mistake.
Change-Id: I864453d16596798e063a2c3569b260fd1a95c209
Signed-off-by: Liang Chen <cl@rock-chips.com>
In the bandwidth tension environment when close win2, vop will access
the freed memory lead to iommu pagefault. so we add this reset to workaround.
Change-Id: I22b0c0f145d042e3aaf98fb45ffff6304c93963c
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Because when enable uboot logo display, vop_crtc_enable() will not be
called when power on, this will lead to some vop initial like
axi channel and some debug irq will not be enabled. so we move some
config to vop_initial() and call from vop_crtc_loader_protect().
Change-Id: I86f02e2e7d12b78cce17e278baaf6dff93137167
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
some version vop unsupport pixel alpha add scale, this case
will lead to display error and post empty.
Change-Id: I32820a14292b46ce61fd30bfccdaa5e4f635de49
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
The most pins of rk3308 are 2bits iomux, but the banks's register
width is 0x8.
Change-Id: I3305810b3f75febd6ec7a933b65e3c9d50f003dd
Signed-off-by: David Wu <david.wu@rock-chips.com>
This adds the necessary data for handling io voltage domains on the rk3308.
As interesting tidbit, the rk3308 contains one iodomain area at grf,
Change-Id: Ife72a284a8926d02ef5df7a422d41924494d0300
Signed-off-by: David Wu <david.wu@rock-chips.com>
Otherwise, clk_gpu won't be disabled actually in the runtime.
Change-Id: I92787a5e23bfb92f5a79efda92c130832751cc3b
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
The commit 9d9491a7da ("mmc: dw_mmc: Fix the DTO timeout calculation")
and commit 4c2357f57d ("mmc: dw_mmc: Fix the CTO timeout calculation")
made changes, which cause multiply overflow for 32-bit systems. The
broken
timeout calculations leads to unexpected ETIMEDOUT errors and causes
stacktrace splat (such as below) during normal data exchange with
SD-card.
| Running : 4M-check-reassembly-tcp-cmykw2-rotatew2.out -v0 -w1
| - Info: Finished target initialization.
| mmcblk0: error -110 transferring data, sector 320544, nr 2048, cmd
| response 0x900, card status 0x0
DIV_ROUND_UP_ULL helps to escape usage of __udivdi3() from libgcc and so
code gets compiled on all 32-bit platforms as opposed to usage of
DIV_ROUND_UP when we may only compile stuff on a very few arches.
Lets cast this multiply to u64 type to prevent the overflow.
Change-Id: I45462bac22f946c5129eab0e0d5b22b3ed7ca19d
Fixes: 9d9491a7da ("mmc: dw_mmc: Fix the DTO timeout calculation")
Fixes: 4c2357f57d ("mmc: dw_mmc: Fix the CTO timeout calculation")
Tested-by: Vineet Gupta <Vineet.Gupta1@synopsys.com>
Reported-by: Vineet Gupta <Vineet.Gupta1@synopsys.com> # ARC STAR
9001306872 HSDK, sdio: board crashes when copying big files
Signed-off-by: Evgeniy Didin <Evgeniy.Didin@synopsys.com>
Cc: <stable@vger.kernel.org> # 4.14
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherry picked from c715160225)
Add the clock tree definition for the new RK3308 SoC.
Change-Id: I1c0794b290207d28102e8d30cca13bbbf54ccfb8
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add the dt-bindings header for the rk3308, that gets shared between
the clock controller and the clock references in the dts.
Change-Id: I9c6ea1228417f07603d89f810726e9cdffd2a10a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.
Change-Id: Ib28b15d3011704a04294672f82d6a8f855da1536
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
