rk3588 frac pll:
FFVCO = ((m + k / 65536) * FFIN) / p
FFOUT = ((m + k / 65536) * FFIN) / (p * 2s)
k is the original code, but the K[15:0] is complement code
(6'b1000_0000_0000_0000 <= K[15:0] <= 16'b0111_1111_1111_1111),
need to be converted.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I107d31d910d260c83891d5b6e927f119761d6fba
1.Set slow slew rate control for PI
2.Set CDR phase path with 2x gain
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: I2d0811b0be7b1d4764ecd738d069b06e4da5eaa2
MUST: after pm_runtime_enable step, any register R/W
should be wrapped with pm_runtime_get_sync/put.
Another approach is to enable the regcache true to
avoid access HW registers.
Alternatively, performing the registers R/W before
pm_runtime_enable is also a good option.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I69dd66230cba636d2ccb31ec01a21be1a482a0e3
MUST: after pm_runtime_enable step, any register R/W
should be wrapped with pm_runtime_get_sync/put.
Another approach is to enable the regcache true to
avoid access HW registers.
Alternatively, performing the registers R/W before
pm_runtime_enable is also a good option.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ife9b1a0e6f75e714bfb6e7c0d472e4603fa8cd8f
The conlock can help to update period and duty when pwm
is working. It takes 10 dclk cycles to make sure lock
works before unlocking.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Id750580b409a24e660d208e80417d4169def02ed
1. Only RGB output in DVI mode.
2. Only HDMI1.4 is supported in DVI mode.
Change-Id: If905a939cdc6602761b2fc235fec7af88e78d307
Signed-off-by: Chen Shunqing <csq@rock-chips.com>
This patch fixes the iomux error for i2s3 lrck and sclk pins.
Change-Id: I0065ab2bd51c9ddfb7f6ed749d1a99601b802260
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Some sensor drivers do not implement enum_frame_interval function, will cause this error
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I63b8a52230b043d5c9ff29db9cb36faed02a7e8f
There are three types of compliance mode test requirement right
now, consolidate them together:
[1] SMA tool: rockchip,compliance-mode = <0 ANY_VALUE_FROM_0_TO_10>;
[2] Soldered board: rockchip,compliance-mode = <mode preset>;
mode: 1->Gen1 2->Gen2 3->Gen3
preset: 0->p0 1->p1 2->p2 .... etc.
[3] lookback: same as SMA tool case
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I180b4881d827e3c2f0fc22f0bab4ca165be44c19
Some device share one pd, but reset control are different.
It should share a reset_group to ensure that one device can
not do reset while anothor is running.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I53527a053d0835085522396e2d9ee649d78325a5
1/ The backlight is for the eDP panel and it has the connector on the
excavator baseboard.
2/ remove cdn_dp
Fixes: 5a2a93f1ee ("arm64: dts: rockchip: move backlight from rk3399 sapphire to excavator")
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I4de565a2658b9a26f7b4155fce03db875703fa0d
The max dclk rate of rgb interface is limited by lcdc
io rate, and that of mcu interface is limited by vop
input rate.
In addition, modify the check of mcu panel, and replace
the flag is_mcu_panel by np_mcu_panel.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I329715aff21f67baf0187cb06b31ffb65f2e9517
rtc compensation value needs to be converted to a bcd code.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ic24a5ba0c31c42b804d1efa65702e680bae26630
Add some delay for some broken card which need long time to
release the remain power leak. 200ms is very safe, no need to
bother device tree property, as it depends on card not board.
Fixes: 60c9e5240f ("mmc: dw_mmc: Add normal and idle pinctrl control")
Change-Id: I5437945cd860674be860d246200e15eed9d91e03
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
rkvdec2_link_power_off():
power_enabled = 0 -> disable irq -> power off
rkvdec2_link_irq():
if power_enabled == 0 -> return and not clear irq
there is a corner case:
1. after power_enabled flag set to 0 and before disable irq
2. irq coming
3. irq return and not clear irq
4. repeat step 2
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I284bf40acb19e0c48cf04e526a534fec6383eb11
In some platform, there are some devices share PD.
If one device is doing pmu idle request to cru reset and
at this time cpu want to read/write reg for the device will crash.
So use the reset_group to prevent the case.
There is a issue that reset_group protected range not enough,
so fix it.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: Ide32966f7cff842e4611213d26901617fd57bc14
If sample_flat field is set to 1, there can't be any sound.
Change-Id: I56ad87d1165fe7d1cc993f9522c4e6d50c253b80
Signed-off-by: Chen Shunqing <csq@rock-chips.com>
There is no length alignment requirement for the last scatterlist.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I9625bce9379cef4c1a8507ba523f5f303d60c9e6
If the time required for a single data calculation exceeds 3 seconds,
timeout occurs.The timeout timer should be reset after the CRYPTO irq
interrupt is triggered.
Change-Id: I21516ba57bfc8eef3b22624e4ed95523d000cee2
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
the deskew fifo works on its own pointers may cause inter-lane skew
to exceed the vesa standard, this poses a risk of errors in dp sink
parsing MSA packet which inserted in data stream
Change-Id: Ia3bdfaed8696c8f7f21f39f0b55d18b1dce7761f
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
For a more stable system, delete the 528MHz frequency and open
the 666MHz frequency ODT.
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I0354c6dde8f39a9b41878446475ee3acbe1be729
Fixes: 6bd92608df ("drm/rockchip: drv: get acm and csc info when boot")
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I0dd41b229fce0c85bd3df03f03b4b40da06ef53a
