MUST: after pm_runtime_enable step, any register R/W
should be wrapped with pm_runtime_get_sync/put.
Another approach is to enable the regcache true to
avoid access HW registers.
Alternatively, performing the registers R/W before
pm_runtime_enable is also a good option.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ib3d5daecad8491f05a3612a2cb02742ec31e4899
MUST: after pm_runtime_enable step, any register R/W
should be wrapped with pm_runtime_get_sync/put.
Another approach is to enable the regcache true to
avoid access HW registers.
Alternatively, performing the registers R/W before
pm_runtime_enable is also a good option.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I9c495361fcb7fb0a06fe1538d05b94617e332756
HWP_EN must be enabled first before block unlock region is set.
Change-Id: I6b107d97de48bb2644da865f353d2adace95224e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
while two camera link to a device tree, if the link relationship is switched from one sensor to another,
there may be error messages in crop information
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I6b6aa3efcf8f862b5b1b6e41fb2b4c2fcead2282
Add 3rd flash id for GD5F1GQ5RExxG to make distinguish with
F50L2G41KA.
Change-Id: I54b65bf631ee5584119bc667f1f6b954789f0f8b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
rk3588 frac pll:
FFVCO = ((m + k / 65536) * FFIN) / p
FFOUT = ((m + k / 65536) * FFIN) / (p * 2s)
k is the original code, but the K[15:0] is complement code
(6'b1000_0000_0000_0000 <= K[15:0] <= 16'b0111_1111_1111_1111),
need to be converted.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I107d31d910d260c83891d5b6e927f119761d6fba
1.Set slow slew rate control for PI
2.Set CDR phase path with 2x gain
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: I2d0811b0be7b1d4764ecd738d069b06e4da5eaa2
MUST: after pm_runtime_enable step, any register R/W
should be wrapped with pm_runtime_get_sync/put.
Another approach is to enable the regcache true to
avoid access HW registers.
Alternatively, performing the registers R/W before
pm_runtime_enable is also a good option.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I69dd66230cba636d2ccb31ec01a21be1a482a0e3
MUST: after pm_runtime_enable step, any register R/W
should be wrapped with pm_runtime_get_sync/put.
Another approach is to enable the regcache true to
avoid access HW registers.
Alternatively, performing the registers R/W before
pm_runtime_enable is also a good option.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ife9b1a0e6f75e714bfb6e7c0d472e4603fa8cd8f
The conlock can help to update period and duty when pwm
is working. It takes 10 dclk cycles to make sure lock
works before unlocking.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Id750580b409a24e660d208e80417d4169def02ed
1. Only RGB output in DVI mode.
2. Only HDMI1.4 is supported in DVI mode.
Change-Id: If905a939cdc6602761b2fc235fec7af88e78d307
Signed-off-by: Chen Shunqing <csq@rock-chips.com>
This patch fixes the iomux error for i2s3 lrck and sclk pins.
Change-Id: I0065ab2bd51c9ddfb7f6ed749d1a99601b802260
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Some sensor drivers do not implement enum_frame_interval function, will cause this error
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I63b8a52230b043d5c9ff29db9cb36faed02a7e8f
There are three types of compliance mode test requirement right
now, consolidate them together:
[1] SMA tool: rockchip,compliance-mode = <0 ANY_VALUE_FROM_0_TO_10>;
[2] Soldered board: rockchip,compliance-mode = <mode preset>;
mode: 1->Gen1 2->Gen2 3->Gen3
preset: 0->p0 1->p1 2->p2 .... etc.
[3] lookback: same as SMA tool case
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I180b4881d827e3c2f0fc22f0bab4ca165be44c19
Some device share one pd, but reset control are different.
It should share a reset_group to ensure that one device can
not do reset while anothor is running.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I53527a053d0835085522396e2d9ee649d78325a5
1/ The backlight is for the eDP panel and it has the connector on the
excavator baseboard.
2/ remove cdn_dp
Fixes: 5a2a93f1ee ("arm64: dts: rockchip: move backlight from rk3399 sapphire to excavator")
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I4de565a2658b9a26f7b4155fce03db875703fa0d
The max dclk rate of rgb interface is limited by lcdc
io rate, and that of mcu interface is limited by vop
input rate.
In addition, modify the check of mcu panel, and replace
the flag is_mcu_panel by np_mcu_panel.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I329715aff21f67baf0187cb06b31ffb65f2e9517
