Solve the problem of insufficient power supply voltage of
USB peripheral
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
Change-Id: I7e06b463a2da567fcf8fa2fc641379d9274ed549
The drm core will disable than enable a crtc when is marked as
connectors_changed.
But when we attach a writeback connector to a running
crtc, we really don't need this disable/enable, which
will black a running screen.
Change-Id: I636615f27424bc60496ffc487c218f60fb95d719
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
According test, if sensor output 2mux mode, cif needs to be
configured BT656_1120_MULTI_ID_MODE_2, nor no interrupts will be
triggered. So BT656_1120_MULTI_ID_MODE_2 & BT656_1120_MULTI_ID_MODE_4
is different, distinguish it.
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: I8e1959131708d2cab87ab086e03023a718f5b807
the poweroff work contains an operation to release the gpu
wake_lock, sometimes, the deferrable work can cause the gpu
wake_lock to be delayed for tens of seconds before release,
the device can not into deepsleep, resulting in increased
power consumption.
Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
Change-Id: I49aba25cfc000739f344420f818c91b382926e6e
Donot pull up BT uart pin before rtl87xx power on.
Signed-off-by: Longjian Lin <llj@rock-chips.com>
Change-Id: I562e4c403f2a56f9253ff677d78d9056cd98a54d
As per UAC1.0 spec Table 4-2: Class-Specific AC Interface
Header Descriptor, the baInterfaceNr(n) are indicated the
interface number of each AudioStreaming. So it needs to
set the baInterfaceNr dynamically according to the interface
IDs allocated by the usb gadget core.
Change-Id: I57cc7b0070fb166aac4360262b2a7e6f2f5df6e1
Signed-off-by: William Wu <william.wu@rock-chips.com>
When system reboot, drm framework will set mode to
prefer mode first then set mode to 0. Clearing flag
in encoder enable will causes the VOP to not set
the sync polarity.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I20dfcc7b6dc76faf903b42620454a7f5071bd3e3
For resolution floating refresh rate such as 59.94 Hz,
the only difference between the resolution and its
corresponding integer refresh rate resolution is the clock.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I149471f58c9eb65f972139b23a45339ea8807e54
1. Add mpp_dev task capacity and default is 1.
The task capacity is the task queue length that hardware can accept.
Default 1 means normal hardware can only accept one task at once.
2. Attach mpp_dev to mpp_taskqueue for status probe. The task queue
capacity is the minimum task capacity of all the attached mpp_dev.
Change-Id: I8cafe806ec9399902237418d2bbcb088240ed415
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
There are some clks(uart) that do not have to comply with the 20 times
fractional divider limit.
Change-Id: I420d8ba3b5de65d9e0ea74920d5ea8450ae94465
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The RK356X DWC3 supports to set the USB 2.0 PHY enter
suspend mode if the DWC3 core suspend conditions are
valid (as per DWC3 controller databook 6.3.46 GUSB2PHYCFG
register bit6). This cause xHC driver failed to send
USB resume signal to USB 2.0 device in xhci_bus_resume().
This patch adds a quirk "xhci-u2-broken-suspend" to force
the xHC to set the link state to XDEV_RESUME and send USB
resume signal to USB 2.0 device.
Change-Id: I24c017867f80728890c0562a12e4554625913e67
Signed-off-by: William Wu <william.wu@rock-chips.com>
Rockchip SNPS xHC 3.0 set USB 2.0 PHY enter suspend mode
from DWC3 core if the suspend conditions are valid (as per
DWC3 controller databook 6.3.46 GUSB2PHYCFG register bit6).
In this case, it needs to set the bus_suspended bit for
USB 2.0, so that in xhci_bus_resume, it can set the xHC
link state to XDEV_RESUME and send USB resume signal to
USB 2.0 device.
Test on RK3568 USB 3.0 Host interface with USB 2.0 Camera
or USB 2.0 HUB which support USB auto suspend. Without this
patch, the xHC fails to send USB resume signal on the USB
bus to wakeup the USB 2.0 devices, and cause xHC died.
Change-Id: Icb5a553d71a5f3144d77f8d5a5132892a5795285
Signed-off-by: William Wu <william.wu@rock-chips.com>
The DWC3 suspend event is used for special usb gadgets
which support usb auto suspend, such as UVC. So disable
the suspend event by default, and enable it depends on
the uwk_en flag. This can avoid printing redundant log
continuously in some case like this:
[47.526109] dwc3 fcc00000.dwc3: device suspend
[47.527118] dwc3 fcc00000.dwc3: device suspend
[47.528200] dwc3 fcc00000.dwc3: device suspend
[47.529110] dwc3 fcc00000.dwc3: device suspend
[47.530120] dwc3 fcc00000.dwc3: device suspend
Change-Id: I1945eba68d4bb1639d9c3ace66a8caea023371cc
Signed-off-by: William Wu <william.wu@rock-chips.com>
On Rockchip platforms, we use TRB_ENT for bulk Tx TRB.
However, the TRB_ENT can only be enabled for TRB if
the transfer length of the TRB is an integer multiple
of the EP maxpacket. The current code only check the
transfer length of the first TRB, it's not enough.
Without this patch, the xHCI fail to do Read(10) command
with the U3 Disk used VFAT filesystem on RK3566 Box board
(2 + 4)G DDR, the error log like this:
[ 23.165539] usb 2-1: new SuperSpeed Gen 1 USB device number 2 using xhci-hcd
[ 23.183342] usb 2-1: New USB device found, idVendor=0781, idProduct=55a3, bcdDevice= 1.00
[ 23.183418] usb 2-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 23.183434] usb 2-1: Product: Ultra Luxe
[ 23.183447] usb 2-1: Manufacturer: SanDisk
...
[ 23.186615] usb-storage 2-1:1.0: USB Mass Storage device detected
[ 23.189013] scsi host0: usb-storage 2-1:1.0
[ 24.217186] scsi 0:0:0:0: Direct-Access SanDisk Ultra Luxe 1.00 PQ: 0 ANSI: 6
[ 24.219712] sd 0:0:0:0: [sda] 120127488 512-byte logical blocks: (61.5 GB/57.3 GiB)
[ 24.221263] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 24.221301] sd 0:0:0:0: [sda] Write Protect is off
[ 24.222162] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 24.243346] sd 0:0:0:0: [sda] Attached SCSI removable disk
[ 24.642325] FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
[ 25.862084] usb 2-1: reset SuperSpeed Gen 1 USB device number 2 using xhci-hcd
[ 25.882974] sd 0:0:0:0: [sda] tag#0 FAILED Result: hostbyte=DID_ERROR driverbyte=DRIVER_OK
[ 25.883003] sd 0:0:0:0: [sda] tag#0 CDB: Read(10) 28 00 00 50 28 01 00 00 3f 00
[ 28.349195] usb 2-1: reset SuperSpeed Gen 1 USB device number 2 using xhci-hcd
[ 28.366763] sd 0:0:0:0: [sda] tag#0 FAILED Result: hostbyte=DID_ERROR driverbyte=DRIVER_OK
[ 28.366823] sd 0:0:0:0: [sda] tag#0 CDB: Read(10) 28 00 01 15 4b 81 00 00 3f 00
Fixes: 0f580acb01 ("usb: xhci: add support for xhci trb ent quirk")
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Iaa8f87eba3146c09fda858704c96644da40f5859
If hdmi mode is changed but not plug out, encoder disabled
is after encoder atomic check, hdmi output_if won't be set
when crtc atomic enable, sync polarity won't be set correctly.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I2e3244c4f8f9f9fd565170d50f39710749085b98
rk3568 CIF_REG_GRF_CIFIO_CON1 reg has been omitted, fix it.
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: Ib489312ae129fd522c7d23f55d14a7852086df25
VOP writeback directly without stride, and the uv buffer is follow
yrgb buffer without gap.
Change-Id: I9f63eb0527499e2d18d99fc248dbfd95b5d6179d
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Esmart/Smart should add offset in y mirror mode.
Change-Id: I5299543006c702c1492ee740460d0b7536e7d6e8
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
1.Fix the problem that MIPI CSI TX is abnormal when HDMI TX is powered on
after rk628.
2.Support dynamic switching of MIPI bit rate.
3.Remove 1080P50 from edid.
Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
Change-Id: I9980065da639b4b269306470f3ffa2db83a9b132
As the frequency can't be changed in isp and dulaview statuses,
the target frequency should be the bigger one, both in isp status
or in dulaview status.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Id9182d591f615304f24ccba5816424a876046dc3
Fixes the following warning:
drivers/devfreq/rockchip_dmc.c:2914
rockchip_dmcfreq_register_cooling_device() warn: passing zero to 'PTR_ERR'
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ia8b0811d0e27394e420b862305917314189f94be
We shouldn't enable any DLL settings in low speed and
always try to reset all of them in case of any leave-out
from previous stage.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Iccd5dde85425d3c5981300da5aba9563b2f8b821
The usb driver will alloc from the cma default memory pool, when it's
limited to 32bit, the cma default memory should limit to dma32.
Change-Id: Ibd91f3158af6eae98d899018685e03e8f47e75a9
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The dwc3 wakeup and suspend interrupt handler are not perfect,
and it can't support usb gadget auto suspend function to save
power. For UVC device, the auto suspend function is necessary
and helpful.
With this patch, it enable DWC3_DEVTEN_EOPFEN by default for
software to handle suspend interrupt. And for Rockchip platforms,
they usually power down DRAM when system enter deep sleep, so
this patch disable the dwc3 irq in dwc3_suspend to avoid dwc3
controller access the DRAM for handling dwc3 event if wakeup
from USB Host resume signal.
By default, the gadget wakeup from system suspend is disabled.
The user can add "wakeup-source" property in DTS dwc3 node to
enable it like this:
&usbdrd_dwc3 {
status = "okay";
wakeup-source;
};
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Iaf9d642ae1ef6ed12e66a15158706de6d73d5124
Avoid image data have 0xff 0x00 0x00 lead to disturb bt1120/bt656
EAV and SAV sync signal, so enable yuv clip when bt1120/bt656 output.
Change-Id: I59d802814f3619641516254b88e82adc636c6cde
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Fix some modes that did not set the U/V address and
cause the output error of the YUV format image.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I41abd364576e0a73fd501f3dfc726eeaa6c9b118
