crypto module should use scmi_clk rather than cru.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: If20d4ab2ff3906564644a89510fed1b25a8a6b1f
For now, new vicap needs this ioctl to obtain channel info.
Change-Id: Ib19345924aa5492b1d999b60cf9fe59faecb6c8e
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
If the transfer finished, auto stop to end this transfer.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I23cd39e63b8ce292a63c9530edde2c9b72c289cb
reason:
if device combo, the device are share the same queue,
which hardware run in different time. thus, these can
also use the same kthread.
Change-Id: I92f6ec4d753b223b55923ae3a243144ba65dc47e
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
According to gki commit 17f9730086 ("ANDROID: GKI: Disable CONFIG_ZONE_DMA on arm64").
After 1a8e1cef76 "arm64: use both ZONE_DMA and ZONE_DMA32" ZONE_DMA
gets enabled by default. Disable this config to remove unused zone.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I555747b4a3aaccb914c7ce2895f08504d2b2dcc2
Modify rk_rng_v1_read to rk_crypto_v1_read.
Modify rk_rng_v2_read to rk_crypto_v2_read.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I0cb094ef7c3cc6915832411e995ffbf0d0d0fbfa
There are two copies of the same power management code
in rk_rng_v1_read and rk_rng_v2_read, moved to rk_rng_read.
Change-Id: I104cf22a8093213a6d22f7a723d3cfaf36aa4414
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
rng module should use scmi_clk rather than cru.
Fixes: b56b10f007 ("arm64: dts: rockchip: rk3588s: add rng node")
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I49994529fcc209c2bc173c1abc497536fb920302
The software utilizes I_COMP and I_BC_LVL interrupts to determine an
attach and what type of port is attached. and I_COMP interrupt also
alerts software that a SRC detach has occurred. So unmask I_COMP for
SRC and I_BC_LVL for SNK.
Fixes: 48242e3053 ("usb: typec: fusb302: Revert "Resolve fixed power role contract setup")
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Ib4cf3b752d0db116f2603d5e1f3ee5c7d114714a
All the digital-fracdiv signoff freq are the same, and up
to 1.5G on rk3588.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Id4b6b43c05b256a2b77d3c6c0603953b7340eca0
As we mask our SDHCI controller as SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
host->max_clk is derived from core clock in the first place. Then
f_max works together with it.
If we adjust loader's core clk setting, such as 50MHz, we will get
50MHz for host->max_clk, because .get_max_clock() reads core clk
when probing driver. That will lead f_max be set to 50MHz as well,
no matter if max-frequency is set higher than 50MHz.
We can simple solve this problem by assigning core clk as 200MHz
in the first place and then let max-frequency property takes over
it.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I25986720fa441da3786ca0904a2d4b1a5b0568e5
1. set CARD_IS_EMMC bit to enable Data Strobe for HS400
2. config the transmit clock source (DLL TX) is original clock input
3. config Command output source and Command output enable are from
register output triggered by clock falling edge
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I5b34fecde7bb1d05211c7d9c42f54c8e154d367e
Picked from ./platform/devicetree/.
This makes GPU utilisation info available and resolve the warning log below:
[ 19.641700][ T83] WARNING: CPU: 0 PID: 83 at drivers/gpu/arm/bifrost/csf/ipa_control/mali_kbase_csf_ipa_control.c:239 kbase_ipa_control_handle_gpu_power_off+0x128/0x198
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
Change-Id: I7ce8d0f52d6340659b2c9ca9692c48043e1060c1
Enable the DP driver used on Rockchip RK3588 SoC.
Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: I4d645edebf90ceaa35b52b0ccf029c17d1a51e67
